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cy8cmbr2110 capsense ? express? 10-button controller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-74494 rev. *a revised september 4, 2012 features register-configurable capsense ? controller ? does not require firmware or device programming ? ten-button solution configurable through i 2 c protocol ? ten general purpose outputs (gpos) ? gpos are linked to capsense buttons ? gpos support direct led drive smartsense? auto-tuning ? maintains optimal button performance even in noisy environment ? capsense parameters dynamically set in runtime ? saves time and effort in device tuning ? wide parasitic capacitance (c p ) range (5 pf?40 pf) advanced features ? robust sensing even with closely-spaced buttons ? flanking sensor suppression (fss) ? user-configurable led effects ? on-system power-on ? on-button touch ? led on time after button release ? standby mode led brightness ? buzzer signal output ? supports analog voltage output (requires external resistors) ? attention line interrupt to host to indicate any capsense but- ton status change ? capsense performance data through i 2 c interface ? simplifies production-line testing and system debug noise immunity ? specifically designed for superi or noise immunity to external radiated and conducted noise ? low radiated noise emission system diagnostics of capsens e buttons ? reports faults at device power-up ? button shorts ? improper value of modulating capacitor (c mod ) ? parasitic capacitance (c p ) value out of range ez-click? customizer tool ? simple graphical configuration options ? dynamically config ures all features ? configurations can be saved and reused later i 2 c interface ? no clock stretching ? supports speed of up to 100 khz wide operating voltage range ? 1.71 v to 5.5 v ? ideal for both regulated and unregulated battery applications low power consumption ? supply current in run mode as low as 23 a [1] for each button ? deep sleep current: 100 na industrial temperature range: ?40 c to +85 c 32-pin quad flat no-leads (qfn) package (5 mm 5 mm 0.6 mm) overview the cy8cmbr2110 capsense express? capacitive touch sensing controller saves time and money, quickly enabling a capacitive touch sensing user interface in your design. it is a register-configurable device and does not require any firmware coding or device programming. in addition, this device is enabled with cypress?s smartsense auto-tuning algorithm which elimi- nates the need to manually tune the user interface during devel- opment and production ramp. this speeds the time to volume and saves valuable engineering time, test time, and production yield loss. the ez-click customizer tool is a simple graphical interface for configuring the device features, through the i 2 c interface. one configuration can be used to configure multiple samples in different boards. the cy8cmbr2110 capsense controller supports up to ten capacitive sensing buttons and ten gpos. the gpo is an active low output controlled directly by the capsense input making it ideal for a wide variety of consumer, industrial, and medical appli- cations. the wide operating range of 1.71 v to 5.5 v enables unregulated battery operation, further saving component cost. the same device can also be used in different applications with varying power supplies. this device supports ultra low-power consumption in both run mode and deep sleep modes to stretch battery life. in addition, this device also supports many advanced features, which enhance the robustness and user experience of the end solution. the key advanced features ar e noise immunity and flanking sensor suppression (fss). noise immunity improves the immunity of the device against radiated and conducted noise, such as audio and radio frequency (rf) noise. fss provides robust sensing even with clos ely-spaced buttons. fss is a critical requirement in sm all form-factor applications. power-on led effects provide visual feedback to the design at system power-on. button-controll ed led effects provide visual feedback on a button touch. these effects improve the aesthetic value of the end product. buzzer signal output provides audio feedback on a button touch. system diagnostics test for design faults at power-on and report any failures. this simplifies production-line testing and reduces manufacturing costs. capsense data output through i 2 c gives critical information about the design, such as button c p and signal-to-noise ratio (snr). this further helps in system debug and production-line testing. note 1. 23 a per button (4 buttons used, 180 button touch per hour, average button touch time of 1000 ms, buzzer disabled, button to uch led effects disabled, 10 pf < c p of all buttons < 20 pf, button scan rate = 541 ms, with power cons umption optimized, noise immunity level normal, csx sensitivi ty medium).
cy8cmbr2110 document number: 001-74494 rev. *a page 2 of 68 contents pinout ................................................................................ 3 typical circuits ................................................................. 4 schematic 1: ten buttons with ten gpos .................. 4 schematic 2: eight buttons with analog voltage output .................................................................... 5 configuring the cy8cmbr2110 . .............. .............. ......... 6 ez-click customizer tool ............................................ 6 device features ................................................................ 6 capsense buttons ...................................................... 6 smartsense auto-tuning ............................................ 6 general purpose outputs (gpos) .............................. 6 toggle on/off ........................................................... 7 flanking sensor suppression (fss) ........................... 7 noise immunity ............................................................ 7 automatic threshold .............. ..................................... 7 led on time .............................................................. 8 button auto reset ............... ........................................ 9 power-on led effects ................................................. 9 button touch led effects ......................................... 11 last button led effect .............................................. 12 standby mode led brightness ................................. 13 latch status read ..................................................... 13 attention/sleep line to host ...................................... 13 analog voltage support ............................................ 14 sensitivity control ...................................................... 15 debounce control ..................................................... 15 buzzer signal output ................................................ 15 host controlled gpos ............................................... 16 system diagnostics ................................................... 16 i2c communication ................ ................................... 17 power consumption and operating modes ................. 20 low-power sleep mode ......... .............. .............. ....... 20 deep sleep mode ...................................................... 20 response time ............................................................... 21 device modes .................................................................. 22 operating mode ......................................................... 22 led configuration mode ........................................... 22 device configuration mode ... .................................... 22 production line test mode ....................................... 22 debug data mode ..... .............. ............... ........... ........ 22 steps to configure cy8cmbr 2110 .............. ............ ..... 23 cy8cmbr2110 reset .............................................. 23 layout guidelines and best practices ......................... 24 capsense button shapes ......................................... 25 button layout design ................................................ 25 recommended via-hole placement .......................... 25 example pcb layout design with ten capsense buttons and ten leds ..................................................... 26 electrical specifications ................................................ 27 absolute maximum ratings ... .................................... 27 operating temperature ............................................. 27 dc electrical characteristics ..................................... 28 ac electrical specifications ....................................... 31 flash write time specifications ................................ 31 capsense specifications .......................................... 32 i2c specifications ...................................................... 32 ordering information ...................................................... 33 ordering code definitions ..... .................................... 33 package information ...................................................... 33 thermal impedance .................................................. 33 solder reflow specifications ..................................... 33 package diagram ...................................................... 34 appendix - register map ............................................... 35 reference information ................................................... 67 acronyms .................................................................. 67 document conventions 67 document history page ................................................. 68 sales, solutions, and legal information ...................... 68 worldwide sales and design s upport ......... .............. 68 products .................................................................... 68 psoc solutions ......................................................... 68
cy8cmbr2110 document number: 001-74494 rev. *a page 3 of 68 pinout table 1. pin diagram and definitions ? cy8cmbr2110 pin label type [2] description if unused 1 cs1 ai capsense button input, controls gpo1 ground 2 cs0 ai capsense button input, controls gpo0 ground 3 gpo0 do gpo activated by cs0 leave open 4 gpo1 do gpo activated by cs1 leave open 5 gpo2 do gpo activated by cs2 leave open 6 gpo3 do gpo activated by cs3 leave open 7 gpo4 do gpo activated by cs4 leave open 8 i2c scl dio i 2 c clock line n/a 9 i2c sda dio i 2 c data line n/a 10 buzzerout0 do buzzer output pin 0/gpo controlled by register settings leave open 11 hostcontrolgpo0 do gpo controlled by register settings leave open 12 v ss p ground n/a 13 hostcontrolgpo1 do gpo controlled by register settings leave open 14 buzzerout1 do buzzer output pin 1/gpo controlled by register settings leave open 15 attention/sleep dio used to control i 2 c communication, device power consumption, and device operating mode v dd 16 gpo5 do gpo activated by cs5 leave open 17 xres di device reset, active high, with internal pull down leave open 18 gpo6 do gpo activated by cs6 leave open 19 gpo7 do gpo activated by cs7 leave open 20 gpo8 do gpo activated by cs8 leave open 21 gpo9 do gpo activated by cs9 leave open 22 cs9 ai capsense button input, controls gpo9 ground 23 cs8 ai capsense button input, controls gpo8 ground 24 cs7 ai capsense button input, controls gpo7 ground 25 cs6 ai capsense button input, controls gpo6 ground 26 cs5 ai capsense button input, controls gpo5 ground 27 cs4 ai capsense button input, controls gpo4 ground 28 v dd p power n/a 29 cs3 ai capsense button input, controls gpo3 ground 30 cs2 ai capsense button input, controls gpo2 ground 31 c mod ai external modulating capacitor, recommended value 2.2 nf (10%) n/a 32 v ss p ground n/a cy8cmbr2110 qfn ( top view ) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 cs 0 cs 1 cs 2 cs 3 cs 4 cs 5 cs 6 cs 7 cs 8 cs 9 gpo 0 gpo 1 gpo 2 gpo 4 gpo 5 gpo 6 gpo 7 gpo 8 gpo 9 cmod xres v ss i2c scl i2c sda bu zze rou t0 buzzerout1 hostcontrolgpo0 atttention\sleep hostcontrolgpo1 v ss v dd gpo 3 note 2. ai ? analog input; di ? digital input; do ? digital output; dio ? digital input / output; p ? power
cy8cmbr2110 document number: 001-74494 rev. *a page 4 of 68 typical circuits schematic 1: ten buttons with ten gpos figure 1. cy8cmbr2110 schematic 1 in figure 1 , the device is configured in the following manner: cs0?cs9 pins: 560 ? to capsense buttons ? ten capsense buttons (cs0?cs9) gpo0?gpo9 pins: led and 5 k ?? to v dd ? capsense buttons drivi ng 10 leds (gpo0-gpo9) c mod pin: 2.2 nf to ground ? modulating capacitor xres pin: floating ? for external reset buzzerout0 pin: to buzzer ? ac buzzer (1-pin) ? buzzer second pin to ground buzzerout1 pin: led and 5 k ? to ground ? used as host controlled gpo hostcontrolgpo0, hostco ntrolgpo1: led and 5 k ? to ground ? two host controlled gpos hostcontrolgpo0, host controlgpo1: floating ? host controlled gpos disabled i2c_sda, i2c_scl pins: 330 ?? to i 2 c header ? for i 2 c communication attention/sleep pin: to host ? for controlling i 2 c communication, power consumption, and device operating mode
cy8cmbr2110 document number: 001-74494 rev. *a page 5 of 68 schematic 2: eight buttons with analog voltage output figure 2. cy8cmbr2110 schematic 2 in figure 2 , the device is configured in the following manner: cs0?cs7 pins: 560 ? to capsense buttons; cs8, cs9 pins: ground ? eight capsense buttons (cs0?cs9) ? cs8 and cs9 buttons not used in design gpo0?gpo7: to external resistive network ? eight gpos (gpo0?gpo7) used for analog voltage output ? gpo8 and gpo9 not used in design c mod pin: 2.2 nf to ground ? modulating capacitor xres pin: floating ? for external reset buzzerout0 and buzzerout1 pins: to ac buzzer ? ac buzzer (2-pin) hostcontrolgpo0, hostcont rolgpo1 pins: led and 5 k ?? to ground ? two host-controlled gpos i2c_sda, i2c_scl pins: 330- ?? to i 2 c header ? for i 2 c communication attention/sleep pin: to host ? for controlling i 2 c communication, power consumption, and device operating mode
cy8cmbr2110 document number: 001-74494 rev. *a page 6 of 68 configuring the cy8cmbr2110 ez-click customizer tool the ez-click customizer tool is a simple and intuitive graphical user interface for efficiently configuring the device. it takes all the required parameters and configures the device accordingly, using i 2 c communication. the configuration can be saved locally on the computer and later re-used by the tool for another design. the tool can also be used to generate a configuration file, which can be used through bridge control panel (refer to an2397 - capsense data viewing tools ) or by the host (in the host firmware) to configure the device. for more details, refer to the ez-click customizer tool user guide . device features capsense buttons supports up to 10 capsense buttons ground the csx pin to disable capsense button input connect a 2.2-nf (10%) capacitor on the c mod pin for proper capsense operation for proper capsense operation, ensure c p of each button is less than 40 pf smartsense auto-tuning supports auto-tuning of capsense parameters does not require manual tuning; all parameters are automati- cally tuned by the device reduces the design cycle time ? no manual tuning ensures portability of the user interface design compensates printed circuit board (pcb) variations, device process variations, and pcb vendor changes general purpose outputs (gpos) gpox pin outputs are strong drive [3] the gpox is controlled by the corresponding csx active low output ? supports si nking configuration for leds (see figure 3 ) if csx is disabled (grounded), then the corresponding gpox must be left floating after power-up on the gpox, a 5-ms pulse is sent after 350 ms (if noise immunity level is ?normal?) and 1000 ms (if noise immunity level is ?high?), if the csx fails the system diagnostics figure 3. example of gpo0 driven by cs0 note 3. when a pin is in strong drive mode, it is pulled up to v dd when the output is high and pulled down to ground when the output is low. cs0 gpo0 button ? touched button ? released table 2. cy8cmbr2110 advanced features feature benefits toggle on/off button retains state after touch (on/off) flanking sensor suppression (fss) avoids multiple button trigger in a design with closely-spaced buttons noise immunity improves device immunity to external noise (such as rf noise) automatic threshold configurable finger threshold for different noise settings led on time gives an led effect on button release button auto reset disables false output trigger when the cond ucting object is placed close to the button power-on led effects and button touch led effects provides visual effects to design at power-on and button touch standby mode led brightness used for led backlighting latch status read no button touch missed by host processor attention/sleep line to host provides device interrupt to host. host c an use this to read data from the device. also controls device operating mode. analog voltage support external resistors can be used with gpos to generate analog voltage output sensitivity control maintains optimal button performance fo r different overlay and noise conditions debounce control prevents false trigger of buttons buzzer signal output provides audio feedback on button touch host controlled gpos gpo pins, which can be controlled by the host processor through i 2 c system diagnostics supports production testing and debugging low-power sleep mode and deep sleep mode low power consumption
cy8cmbr2110 document number: 001-74494 rev. *a page 7 of 68 toggle on/off toggles the gpo state at each button touch (see figure 4 ). use for mechanical button repl acement (for example, wall switch). toggle feature can be enabled on each capsense button individually. flanking sensor suppression (fss) allows only one button to be in the touch state at a time. you can distinguish touch states for closely spaced buttons. if a finger contacts multiple buttons, only the first one to sense a touch state turns on. also used in situations when a button can produce opposite effects. for example, an interface with two buttons for brightness control (up or down). fss can be enabled for each button individually. this helps to enable fss only for those buttons which are closely spaced. for example, if a design has ten buttons with six buttons closely-spaced, fss can be enabled just for those six buttons. fss action can be explained for the following scenarios: 1. when only one button is touch ed, it is reported as on (see figure 5 ). 2. when more than one button is detected as on, and previously one of those buttons was to uched, then the button touched previously is reported as on (see figure 6 ). noise immunity improves the immunity of the device against external radiated and conducted noise. reduces the radiated noise emission. possible noise immunity levels are ?normal? and ?high?. select ?high? only in a high -noise environment because it increases device power cons umption and response time. automatic threshold button signal is compared to finger threshold for gpo output finger threshold is configurable; valid range is 50-245 counts used to determine button on/off state for different noise conditions you can configure finger threshold to be set automatically to learn more about finger threshold, refer to section 2.3 in getting started with capsense figure 4. example of togg le on/off feature on gpo0 figure 5. fss when one button is touched figure 6. fss when multiple buttons are touched with one button on previously cs0 gpo0 no button is on prior to the touch cs1 is reported as on upon touch cs1 is touched; reported on cs2 also touched along with cs1; cs1 is reported on
cy8cmbr2110 document number: 001-74494 rev. *a page 8 of 68 led on time provides a variable amount of led on time (upto 5100 ms) after a button is released. the gpox is driven low for a spec ified interval after the corre- sponding csx button is released (see figure 7 ). when a button is reset (refer to button auto reset on page 9 ), led on time is not applied on the corresponding gpo. applicable to the gpo of the last button released in figure 8 , gpo0 goes high prematurely (prior to led on time expiration) because cs1 button is released. therefore, the led on time counter is reset. now, the gpo1 remains low for led on time after releasing cs1. led on time can range from 0-5100 ms. led on time resolution is 20 ms. led on time is disabled if toggle on/off is enabled. figure 7. example led on timing diagram on gpo0 figure 8. example led on timing diagram on gpo0 and gpo1 cs0 gpo0 led ? on ? time cs0 gpo0 cs1 gpo1 start ? led ? on ? time ? counter restart ? led ? on ? time ? counter reset ? led ? on ? time ? counter led ? on ? time
cy8cmbr2110 document number: 001-74494 rev. *a page 9 of 68 button auto reset prevents a stuck button due to a metal object placed close to that button. useful when the button is kept on only for a specific period of time. if enabled, button is considered off after the button auto reset period, even though the button continues to be touched. see figure 9 . auto reset period can be set to 5 or 20 seconds. power-on led effects provides a visual effect at device power-up. after power-on, all the leds show dimming and fading effects for an initial time. seen on gpox when csx is enabled. the gpos are configured in groups to have the same param- eters. the groups are: ? gpo1, gpo2, gpo3 ? gpo4, gpo5, gpo6 ? gpo7, gpo8, gpo9 gpo0 can be configured separately. useful in designs with a special use for cs0 button, such as a power button. all capsense buttons are disabled during this time. if any capsense button (csx) fails the power-on self test, then these effects are not seen on the corresponding gpox. to know more about power-on self test, refer system diagnostics on page 16 . the following parameters are set for led effects: ? low brightness ? minimum led intensity ? low-brightness time ? the time period for which the led remains in a low-brightness state ? ramp-up time ? the time period during which the led tran- sitions from low brightness to high brightness ? high brightness ? maximum led intensity ? high-brightness time ? the time during which the led stays in a high-brightness state ? ramp-down time ? the time it takes the led to go from high brightness to low brightness ? repeat rate ? the number of times the effects are repeated brightness levels can range from 0 to 100 percent. the time range can be 0 to 1600 ms. high-brightness level must be more than low-brightness level. the effects are seen after the device initialization time from power-on. this time is less than 350 ms (if the noise immunity level is ?normal?) and less than 1000 ms (if the noise immunity level is ?high?). the pattern can be set to occur sequentially or concurrently on all the gpos (see figure 10 and figure 11 on page 10 ). during power-on led effect s, the device acks i 2 c communi- cation but all write commands are ignored. the host can only read operating mode data. figure 9. example of button auto reset on gpo0 cs0 gpo0 auto ? reset ? period gpo0 ? not ? driven ? as ? cs0 ? is ? considered ? to ? be ? off button ? is ? touched ? for ? more ? than ? the ? auto ? reset ? period
cy8cmbr2110 document number: 001-74494 rev. *a page 10 of 68 figure 10. example power-on led effects (con current on all gpos) with repeat rate = 1 [4] figure 11. example power-on led effects (sequential) with two-button design and repeat rate = 0 [5] gpox ? led ? brightness 90% r a m p ? u p r a m p ? d o w n 10% 500 ? ms 200 ? ms 500 ? ms 200 ? ms power ? on = ? (350 ? ms/ 1000 ? ms) 90% r a m p ? d o w n 10% 500 ? ms 200 ? ms 500 ? ms 200 ? ms r a m p ? u p normal ? operation effects ? completed 0% = ? (3150 ? ms ? / ? 3800 ? ms) 0% 10% notes 4. ramp up time = 500 ms; high brightness = 90%; high brightness time = 200 ms; ramp down time = 500 ms; low brightness = 10%; l ow brightness time = 200 ms; repeat rate = 1 5. ramp up time = 300 ms; high brightness = 100%; high brightness time = 100 ms; ramp down time = 300 ms; low brightness = 10%; low brightness time = 100 ms; repeat rate = 0 gpo0 ? led ? brightness ra m p ? u p r a m p ? d o w n 300 ? ms 300 ? ms power ? on <= ? 350ms/ 1000 ? ms normal ? operation effects ? completed gpo1 ? led ? brightness <= ? 1950 ? ms ? / ? 2600 ? ms 0% 0% 0% 100% 100 ? ms 10% 100 ? ms r a m p ? d o w n 100% 10% r a m p ? u p 300 ? ms 300 ? ms 100 ? ms 100 ? ms 0% 10% 10%
cy8cmbr2110 document number: 001-74494 rev. *a page 11 of 68 button touch led effects provides a visual feedback on a button touch. improves the aesthetic value of the design. seen on gpox when csx is touched. the gpos are configured in groups to have the same param- eters. the groups are: ? gpo1, gpo2, gpo3 ? gpo4, gpo5, gpo6 ? gpo7, gpo8, gpo9 gpo0 can be configured separately. useful in designs with a special use for the cs0 button, such as the power button. the following parameters can be set for the effects: ? low brightness ? minimum led intensity ? low-brightness time ? the time period during which led remains in a low-brightness state ? ramp-up time ? the time period during which the led tran- sitions from low brightness to high brightness ? high brightness ? maximum led intensity ? high-brightness time ? the time during which the led stays in a high-brightness state ? ramp-down time ? the time it takes the led to go from high brightness to low brightness ? repeat rate ? the number of times the effects are repeated brightness levels can range from 0 to 100 percent. the time range can be 0 to 1600 ms. high-brightness level should be more than the low-brightness level for proper visual effects. button touch led effects can be of two types (see figure 12 on page 11 ): ? breathing effects: when the breathing effect is enabled, led intensity changes from standby mode led brightness to low brightness immediately after a button touch. it then ramps up to high-brightness and stays for high brightness time. it then ramps down to low brightness and stays for low bright- ness time. this effect repeats for the duration during which the button is touched. when the button is released, the led effects cycle that is in progress, continues. after this cycle completes, the led effects cycle may repeat depending on the repeat rate. ? non-breathing effects: when the br eathing effect is disabled, the led intensity changes from standby mode led bright- ness to low brightness immediately after a button touch. it then ramps up to high brightness and stays there for the duration during which the button is touched. when the button is released, the led maintains its state for high brightness time. it then ramps down to low brightness and stays for low brightness time. this effect may then repeat depending on the repeat rate. if the button touch led effects are active on one gpox and the corresponding csx is touc hed again, then the pattern restarts on gpox. if the toggle on/off effect is also enabled, the leds toggle between standby mode led brightness and high brightness on successive button touches (see figure 13 on page 12 ). if button touch led effects are enabled, the led on time is automatically disabled. when the device goes to deep sleep, ongoing button touch led effects are immediately disabled. figure 12. button touch led effect pattern [6] button button ? touched button ? released intensity ? with ? breathing ? effect ? enabled r e p e a t s ? f o r ? n ? t i m e s ? a s ? s p e c i f i e d ? b y ? r e p e a t ? r a t e high ? brightness r a m p ? u p r a m p ? d o wn low ? brightness t ru t h t rd t l intensity ? with ? breathing ? effect ? disabled repeats ? for ? n ? times ? as ? specified ? by ? repeat ? rate high ? brightness r a m p ? u p r a m p ? d o w n low ? brightness t ru t h t rd t l high ? hold ? time note 6. t ru ? ramp up time; t rd ? ramp down time; t h ? high brightness time ; t l ? low brightness time
cy8cmbr2110 document number: 001-74494 rev. *a page 12 of 68 figure 13. button touch led effects with toggle enabled last button led effect button touch led effects can be configured to be interrupted on one gpo if any other button is touched. the effects reset on the firs t gpo and start on the gpo associated with the la st button touched (see figure 14 ). this feature is disabled by default. if toggle on/off is also enabled for some buttons, last button led effect is disabled for those buttons. if the flanking sensor suppression (fss) feature is also enabled, and two buttons are touched simultaneously, the last button led effect does not apply because the second button touched does not turn on. figure 14. button touch led effects (breathing) with last button led effect enabled button button ? touched button ? released intensity ? high ? brightness r a m p ? u p r a m p ? d o w n t ru t rd standby ? mode ? led ? brightness button ? touched button ? released standby ? mode ? led ? brightness cs1 gpo0 ? led ? brightness high ? brightness r a m p ? u p r a m p ? d o w n low ? brightness t ru t h t rd t l gpo1 ? led ? brightness cs0 cs0 ? touched cs1 ? touched r e p e a t s ? f o r ? n ? t i m e s ? a s ? s p e c i f i e d ? b y ? r e p e a t ? r a t e high ? brightness r a m p ? u p r a m p ? d o w n low ? brightness t ru t h t rd t l cs1 ? released cs0 ? released
cy8cmbr2110 document number: 001-74494 rev. *a page 13 of 68 standby mode led brightness provides a better visual feedback for buttons when in off state. improves the aesthetic value. the led associated with gpox is in standby mode led brightness after the conclusion of button touch led effects, when csx is off. standby mode led brightness can be configured to be 0%, 20%, 30%, or 50%. standby mode led brightness increases device power consumption because the device does not go to low power sleep. standby mode led brightness is disabled when the device goes to deep sleep. latch status read host processor can check the capsense button status by reading the register map through i 2 c communication. when a button is touched, the dev ice generates an interrupt to host through the attention/sleep line. host can then read csx status. if the interrupt is not serviced immediately, and the button is released before the interrupt is serviced, the host can miss that button touch. to avoid missing any button touch, the host should read both current status (cs) and latch status (ls). cs is stored in the bu tton_current_stat0 and button_current_stat1 registers in operating mode . ls is stored in the button_latch_stat0 and button_latch_stat1 registers in operating mode . to know more about these registers, refer to operating mode . table 3 on page 13 lists the various possibilities of button touch acknowledge/miss. these are shown in figure 15 and figure 16 . figure 15. latch status read 1 figure 16. latch status read 2 attention/sleep line to host bidirectional active low line; can be controlled by both the device and the host. the attention/sleep line is in the open drain low drive mode the device is in the low-power sleep mode by default (if the attention/sleep line is high). for more inform ation, refer to the section low-power sleep mode on page 20 . the device cannot go to the low-power sleep mode if the attention/sleep line is low. attention/sleep line should be pulled low only if required, to reduce device power consumption. attention/sleep line can be used for the following functions: device interrupt to host on any button touch, the device pulls the attention/sleep line low to indicate an inte rrupt to the host (see figure 17 ). if more than one button is touc hed simultaneously, the attention line is pulled low for the entire duration of any button touch (see figure 18 ). the attention/sleep line goes high when the button is released. table 3. latch status read current status (cs) latch status (ls) comments 0 0 csx is not touched during the current i 2 c read; host has already acknowl- edged any previous csx touch in the last i 2 c read. 0 1 csx was touched before the current i 2 c read; this csx touch was missed by the host. 1 0 csx was touched and acknowledged by the host during the previous i 2 c read; the same csx is still touched during the current i 2 c read. 1 1 csx is touched during the current i 2 c read. cs ? = ? 0 ls ? = ? 1 current ? status i 2 c ? read i 2 c ? read latch ? status cs ? = ? 0 ls ? = ? 0 cs ? = ? 0 ls ? = ? 0 current ? status i 2 c ? read i 2 c ? read latch ? status i 2 c ? read cs ? = ? 1 ls ? = ? 1 cs ? = ? 1 ls ? = ? 0
cy8cmbr2110 document number: 001-74494 rev. *a page 14 of 68 figure 17. attention/sleep line with csx buttons touched separately figure 18. attention/sleep line with csx buttons touched simultaneously i 2 c communication attention/sleep line should be pulled low before any i 2 c communication is initiated. if the attention/sleep line is high, the device may nack i 2 c communication. when the attention/sleep line is low, the device may nack i 2 c communication, but very infrequently. deep sleep mode to enable the deep sleep mode, the host needs to set the ?deep sleep? bit in host_mode register (in the operating mode). the host needs to wait for 50 ms and then pull attention/sleep line high. host should pull the attention/sleep line low for the device to wake up from deep sleep. for more information, refer to the section deep sleep mode on page 20 . analog voltage support a general external resistive ne twork with a host processor is shown in figure 19 . host can be configured to perform different functions based on the voltage level at input pins. th is is controlled by switches. these switches can be cont rolled by capsense buttons. if enabled, gpos replace these switches in the network. gpos are in the open drain low drive mode. gpos cannot be used for the re sistive network and led drive simultaneously. if only one button needs to be on for analog voltage support, fss should be enabled. for cy8cmbr2110, a simple external resistive network is shown in figure 20 . figure 19. general exte rnal resistive network figure 20. analog voltage support for cy8cmbr2110 attention/sleep ? line cs1 cs0 touch ? cs1 touch ? cs0 release ? cs1 release ? cs0 attention /sleep ? line cs1 cs0 touch ? cs0 touch ? cs1 release ? cs1 release ? cs0 host ? processor v dd v dd r 1 r 2 r 3 r 4 r 7 r 6 r 8 r 5 key ? 1 key ? 2 host ? processor v dd v dd r 1 r 2 r 3 r 4 r 7 r 6 r 8 r 5 key ? 1 key ? 2 gpo2 gpo1 gpo3 gpo4 gpo6 gpo5 gpo7 gpo8
cy8cmbr2110 document number: 001-74494 rev. *a page 15 of 68 sensitivity control sensitivity of each button can be set individually. use higher sensitivity setting when the overlay thickness is higher or if the button diameter is small. use a lower sensitivity settin g when power consumption needs to be low. possible sensitivity settings are ?high?, ?medium?, and ?low?. debounce control avoids false triggering of buttons due to noise spike or any other glitches in the system. specifies the minimum time for which a button has to be sensed as touch, for an output trigger. debounce value can range from 1 to 255. debounce value can be set separately for cs0 and combined for cs1 to cs9. this is useful for additional functions, such as, linking system reset to touch time corresponding to cs0 debounce. the device response time depends on the button debounce. refer to response time on page 21 . ta b l e 4 lists some examples of device response time for different debounce values. [7] buzzer signal output gives audio feedback for a button touch. for more details, refer to response time on page 21 . buzzer signal output can have two configurations: ac 1-pin and ac 2-pin. in the ac 1-pin buzzer configuration, the buzzer must be connected to the buzzerout0 pin (see figure 21 ). a square wave of the given frequency and duty cycle is driven on this pin. the buzzerout1 pin can either be left floating or configured as a host-controlled gpo. figure 21. ac 1-pin buzzer configuration in ac 2-pin buzzer configuration, connect the buzzer between the buzzerout0 and buzzerout1 pins (see figure 22 ). two out-of-phase square waves of the given frequency and duty cycle are driven on these pins. figure 22. ac 2-pin buzzer configuration if the buzzer is not used, then both the pins can be used as host-controlled gpos. table 5 shows the possible buzzer settings. the idle state of the buzzer pin can be configured to be either v dd or ground. the buzzer pin is driven to the idle state when no button is touched, or after the buzzer on time elapses, even when the button is kept touched (see figure 23 ). the buzzer signal frequency is configurable and can assume one of the following values (in khz) ? 1.00, 1.14, 1.33, 1.60, 2.00, 2.67, 4.00 the buzzer output is driven for the configured time and does not depend on the button touch time. buzzer on time has a range of (1 to 127) button scan rate constant. to know more about bu tton scan rate constant, refer to power consumption and operating modes on page 20 . buzzer signal output is strong drive. the output is driven commonl y by all the csx buttons. buzzer output restarts if any button is touched before the buzzer on time expiration (see figure 24 ). table 4. example response times for debounce values debounce value response time for consecutive button touch (ms) 170 4105 7140 10 175 100 1225 200 2380 255 3010 cy8cmbr2110 buzzerout0 buzzer depends ? on ? buzzer ? specification buzzerout1 cy8cmbr2110 buzzerout0 buzzerout1 buzzer note 7. 8-buttons, noise immunity level no rmal, response time optimized design.
cy8cmbr2110 document number: 001-74494 rev. *a page 16 of 68 figure 23. buzzer time-out figure 24. buzzer terminated and restarted host controlled gpos two gpo pins (hostcontrolgpo0, hostcontrolgpo1) are available whose logic states can be controlled by the host. if the buzzer is not used, then up to two more host-controlled gpos are available (using bu zzerout0 and buzzerout1 pins). the host can control these gpos in the operating mode, production line test mode, and debug data mode. host-controlled gpos are in low state at power-on. host-controlled gpo settings cannot be saved to flash and must be configured after reset. hostcontrolgpo1 has a positive going pulse of 16 ms during power-on. these outputs are in strong drive mode. table 5 shows the maximum available host-controlled gpos, depending on the buzzer configuration. system diagnostics a built-in power-on self test (post) mechanism performs some tests at power-on reset (por), which can be useful in production testing. if any button fails these tests, a 5-ms pulse is sent out on the corresponding gpo within 350 ms (if noise immunity level is ?normal?) or 1000 ms (if noise immunity level is ?high?) after por. to know the system diagnostics result, the host can read device data in production line test mode through the i 2 c interface. since the host can read data through i 2 c lines, there is no need to interface gpos to the host. the following tests are performed on all the buttons. button shorted to ground if any button is shorted to ground, it is disabled. for an accurate detection of button shorted to ground, the resistance between the csx pin and ground should be less than the limits specified in table 6 . figure 25. button shorted to ground table 5. buzzer and hos t-controlled gpo settings buzzer configuration buzzerout0 pin buzzerout1 pin max available host controlled pos no buzzer floating/hos t controlled gpo3 floating/hos t controlled gpo2 4 ac 1-pin buzzer buzzer pin 0 floating/hos t controlled gpo2 3 ac 2-pin buzzer buzzer pin 0 buzzer pin 1 2 cs0 buzzer signal ? output buzzer ? on ? time cs0 ? kept ? touched cs1 buzzer ? signal ? output buzzer ? on ? time cs1 ? touched cs0 ? touched buzzer ? output ? restarted cs0 table 6. maximum resistance between csx and gnd for proper system diagnostics operation power supply (v dd ) (v) max resistance between csx and gnd ( ? ) 5.5 680 5760 1.8 1700 cy8cmbr2110 button shorting
cy8cmbr2110 document number: 001-74494 rev. *a page 17 of 68 button shorted to v dd if any button is shorted to v dd , it is disabled. figure 26. button shorted to v dd button to button short if two or more buttons are shorted to each other, all of these buttons are disabled. figure 27. button to button short improper value of c mod recommended value of c mod is 2 nf to 2.4 nf. if the value of c mod is less than 1 nf or greater than 4 nf, all the buttons are disabled. button c p > 40 pf if the parasitic capacitance (c p ) of any button is more than 40 pf, that button is disabled. figure 28. example showing cs0 and cs1 passing the post and cs2 and cs3 failing in figure 28 , cs0 and cs1 are enabled; cs2 and cs3 are disabled because they failed the post. therefore, a 5-ms pulse is observed on gpo2 and gpo3. i 2 c communication i 2 c is the interface used to communicate between the cy8cmbr2110 (i 2 c slave) and the host (i 2 c master). it uses a simple two-wire synchronous communication protocol. these two wires are: 1. serial clock (scl) ? this line is used to synchronize the slave with the master. 2. serial data (sda) ? this line is used to send data between the master and the slave. the cy8cmbr2110 can be a part of a one-slave or a multi-slave environment. see figure 29 and figure 30 . figure 29. i 2 c communication between one master and one slave figure 30. i 2 c communication between one master and multiple slaves the cy8cmbr2110 i 2 c interface has the following features: 1. bit rate up to 100 kbps 2. configurable i 2 c slave address (0?127), with default slave address as ?37h?. 3. hardware address compare 4. no bus-stalling ? no clock stretching 5. i 2 c buffer mode (32-byte hardware buffer) 6. register-based access to i 2 c master for read and write opera- tions. cy8cmbr2110 button shorting v dd cy8cmbr2110 button shorting button 5ms ? pulse gpo3 gpo2 gpo1 (high) gpo0 (high) 5ms ? pulse i 2 c ? master (host) i 2 c ? slave (cy8cmbr2110) scl sda v dd rr i 2 c ? master (host) i 2 c ? slave ? 1 scl sda v dd rr i 2 c ? slave ? 2 i 2 c ? slave ? 3 cy8cmbr2110 other ? slave ? devices ? on ? the ? bus
cy8cmbr2110 document number: 001-74494 rev. *a page 18 of 68 i 2 c slave address to uniquely identify each device in a multi-device state, an i 2 c slave address is used. this address is a 7-bit value, which allows up to 127 slaves on the bus simultaneously. when the bus master wants to communicate with a slave on the bus, it sends a start condition followed by the i 2 c address of the relevant slave. the start condition alerts all slaves on the bus when a new transaction starts. the sl ave with the specified i 2 c address acknowledges the master. all the other slaves ignore all further traffic on the bus until the next start condition is detected. start and stop conditions the master initiates the communication by issuing a start condition on the bus and termin ates the communication by issuing a stop condition. the bus is considered busy between these two conditions. see figure 31 . a start condition is shown by changing the level of sda line (from high to low), when the scl line is high. a stop condition is shown by changing the level of sda line (from low to high), when the scl line is high. figure 31. i 2 c start and stop conditions figure 32. i 2 c interface between host and device i 2 c communication guidelines for cy8cmbr2110 1. the attention/sleep line should be pulled low by either the host or the device, before initiating any i 2 c communication. 2. the host needs to wait for 350 ms (if noise immunity level is ?normal?) or 1000 ms (if noise i mmunity level is ?high?) after device power-on, before initiating any i 2 c communication. else, the device nacks any such communication. 3. the host needs to wait for a minimum of 60 ms after any i 2 c transaction before initiating a new transaction. 4. host needs to wait for 350 ms (if noise immunity level is ?normal?) or 1000 ms (if noise i mmunity level is ?high?) after ?save to flash? and ?software reset? commands are issued before initiating any further transaction. 5. in run time the device should be in operating mode. 6. the host should not initiate a new start condition for the device, without a stop condition for the previous i 2 c communication (also called repeat start condition). 7. host needs to maintain a minimum of 60 ms between any two i 2 c transactions a. if the host does not maintain this time while reading, then it gets the same data as read in previous transaction. b. if the host writes to the same register twice within this time, then the old data is lost. c. if the host writes to different registers within this time (reg x in first write and reg y in se cond write) then the data is not lost. write operation for a write operation, the following steps are performed: 1. the host sends the start condition to the device on the sda line. 2. the host specifies the slave a ddress, followed by r/w bit to specify a write operation. t he device acks the host. 3. the host specifies the register ad dress to which it has to write. the device acks the host. 4. the host starts sending the data to the device, which is written to the register address specified by the host. this is followed by an ack from the device. 5. if the write operation includes more bytes, each following byte is written to the successive register address. each successive byte is followed by an ack from the device. 6. after the write operation is complete, the host sends the stop condition to the device. this marks the end of the communication. see figure 33 on page 19 . notes 1. the host must not write to a read only register. 2. the host can write a maximum of 32 bytes in one i 2 c trans- action. scl sda start stop host cy8cmbr2110 cs0 cs1 cs9 attn/sleep scl sda v dd v dd v dd
cy8cmbr2110 document number: 001-74494 rev. *a page 19 of 68 figure 33. host writing x bytes to the device setting the device data pointer the host sets the device data pointer to specify the starting point for future read operations. to set the device pointer, perform the following steps: 1. the host sends the start condition to the device on the sda line. 2. the host specifies the sl ave address on the sda line, followed by the read/write bit to specify a write operation. the device acks the host. 3. the host specifies a register ad dress (this register address is always 00). any future read operations start from this address in the device. the device acks the host. 4. the host sends the stop conditi on to the device. this marks the end of the communication. see figure 34 . figure 34. host setting the device data pointer read operation for a read operation, perform the following steps: 1. the host sends the start condition to the device on the sda line. 2. the host specifies the slav e address, followed by the read/write bit to specify a read operation. the device acks the host. 3. the device retrieves the byte fr om the register address 00 and sends it to the host. t he host acks the device. 4. each successive byte is retrieved from the successive register address and sent to the host, followed by acks from the host. 5. after the host has received the required bytes, it nacks the device. 6. the host sends the stop conditi on to the device. this marks the end of the communication. see figure 35 . figure 35. host reading x bytes from the device legend for i 2 c electrical specifications of the device, refer to the i2c specifications . slave address ` register ? address ? (n) data[n] data[n+1] data[n+x] s a 6 a 5 a 4 a 3 a 2 a 1 a 0 r w a r 7 r 6 r 5 r 4 r 3 r 2 r 1 r 0 a d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a p ack ack ack ack ack write start stop s a 6 a 5 a 4 a 3 a 2 a 1 a 0 r w a 00000000 a p slave address ` register ? address ack ack write start stop slave address ` data[1] data[3] data[x] ack ack ack ack nack read start stop s a 6 a 5 a 4 a 3 a 2 a 1 a 0 r w a d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 np data[2] cy8cmbr2110 ? to ? host host ? to ? cy8cmbr2110
cy8cmbr2110 document number: 001-74494 rev. *a page 20 of 68 power consumption and operating modes cy8cmbr2110 can meet low-power requirements of battery-powered applications. to design for the lowest operating current, do the following: ground all unused capsense inputs (csx). minimize c p using the design guidelines in getting started with capsense , section 3.7.1. reduce supply voltage (valid range: 1.71 v to 5.5 v). reduce the sensitivity of csx buttons. configure the design to be optimized for power consumption. use ?high? noise immunity level only if needed. use a higher button scan rate or deep sleep operating mode. to know more about the steps to reduce power consumption, refer to section 5 in the cy8cmbr2110 design guide . low-power sleep mode the following flowchart describes the low-power sleep mode operation. the button scan rate is equal to the sum of the time the device scans and sleeps. the register settings define a button scan rate offset. the offset is added to a constant to get the button scan rate. the constant is given in table 7 . the range of scan rate is 25 to 561 ms. figure 36. low power sleep mode operation deep sleep mode to enable the deep sleep mode, connect the attention/sleep line to the host as shown in figure 37 ; the host should perform the following steps: ? pull the attention/sleep line low ? set the deep sleep bit in the host_mode register (in oper- ating mode) high ? wait for 50 ms ? pull the attention/sleep line high figure 37. attention/sleep pin connection to enable deep sleep mode in deep sleep mode, all blocks are turned off and the device power consumption is 0.1 a. there is no capsense scanning in deep sleep mode. after the device enters deep sleep mode, the ?deep sleep? bit is automatically cleared. the attention/sleep line should be pulled low for the device to wake up from deep sleep. when device comes out of deep sleep mode, the capsense system is re-initialized. the typi cal time for re-i nitialization is 20 ms (normal noise immunity level) or 50 ms (high noise immunity level). any button touch within this time is not reported. the deep sleep bit cannot be set by ez-click customizer tool and must be set by an external i 2 c communication to the device. scan all buttons with button scan rate constant no button touched for 15 secs? yes scan all buttons with user defined button scan rate is any button active? yes no no scan all buttons with button scan rate table 7. button scan rate constant button count button scan rate constant response time optimized design power consumption optimized design noise immunity level ?normal? noise immunity level ?high? noise immunity level ?normal? noise immunity level ?high? 5 25 ms 35 ms 35 ms 55 ms > 5 35 ms 55 ms 35 ms 55 ms cy8cmbr2110 host controller attention/sleep digital i/o pin
cy8cmbr2110 document number: 001-74494 rev. *a page 21 of 68 response time response time is the minimum amount of time the button should be touched for the devi ce to detect as a valid button touch. it is given by the following equations: 1. if noise immunity level is ?normal? . 2. if noise immunity level is ?high?. where rt cbt is response time for consecutive button touch after first button touch rt fbt is response time for first button touch debounce for cs1-cs9 can be from 1 to 255 debounce for cs0 can be from 1 to 255 round down is the greatest integer less than or equal to ((debounce ? 1)/3) refer to table 7 on page 20 to obtain button scan rate constant. for example, consider an eight-but ton, response time-optim ized design with the button scan ra te offset set to 391 ms. the noise immunity level is set to normal. let us assume that cs0 is not used in th e design and the debounce value for each button (cs1?cs8) is set as 3. the button scan rate constant for such a design is 35 ms (see table 5 on page 16 ), which results in a button scan rate to be (35 + 391 ms) 426 ms. the response time for such a design is given as:
cy8cmbr2110 document number: 001-74494 rev. *a page 22 of 68 device modes the register map is divided into five modes. operating mode led configuration mode device configuration mode production line test mode debug data mode the following sections give an overview of each mode. each register mode consists of different sets of registers. refer to the appendix - register map section for description of all the registers in detail. operating mode the host must use this mode after configuring the device in run time. the following can be configured in this mode: 1. host control gpo logic levels 2. deep sleep mode entry 3. software reset 4. device mode change host can read the following device information in this mode: 1. capsense current and latched status 2. current configuration (factory default or user configuration) 3. flash checksum 4. ram checksum 5. device id and firmware revision led configuration mode the host must use this mode to configure the device and revert back to the operating mode after configuration. the host can configure the following in this mode: 1. analog voltage output settings 2. power-on led effects 3. button touch led effects 4. led on time 5. standby mode led brightness 6. device mode change device configuration mode the host must use this mode to configure the device and then revert back to operating mode afte r configuration is done. host can configure the following in this mode: 1. i 2 c address 2. fss group buttons 3. toggle on/off option 4. button sensitivity, debounce, finger threshold 5. buzzer settings 6. automatic threshold settings 7. button scan rate settings (power settings) 8. noise immunity settings 9. button auto reset time 10.design optimization settings 11.save settings to flash 12.load factory default configuration 13.device mode change production line test mode the host must use this mode only during the design validation and production testing stage of product development. the host can configure the following in this mode: 1. host-controlled gpo logic levels 2. changing device mode the host can read the following device information in this mode, which helps in production line test: 1. system diagnostics data ? button short to ground ? button short to another button ? button short to v dd ? button parasitic capacitance > 40 pf ? improper value of c mod value connected 2. all buttons snr values 3. valid button count 4. capsense current status debug data mode the host must use this mode only during the design validation stage of product development. the host can configure the following in this mode: 1. host-controlled gpo logic levels 2. parameter type and button number, which the host wants to debug 3. changing device mode the host can read the following device information in this mode, which helps in design validation: 1. capsense raw data (raw count, baseline and signal) 2. capsense button snr 3. button parasitic capacitance 4. capsense current status
cy8cmbr2110 document number: 001-74494 rev. *a page 23 of 68 steps to configure cy8cmbr2110 to configure the cy8cmbr2110, follow these steps: 1. change device mode to led configuration mode. 2. wait for 55 ms. 3. write to all the configurati on registers in the led configu- ration mode. 4. wait for 55 ms. 5. change device mode to device configuration mode. 6. wait for 55 ms. 7. write to all the configuration registers in the device configu- ration mode. 8. calculate checksum and enter this value in the registers. checksum (checksum_msb (0x1e) and checksum_lsb (0x1f) in the device configuration mode): checksum is the sum of values of the registers (0x01?0x1f) in the led configuration mode and the registers (0x01?0x1d) in the device configuration mode. checksum also takes the valu es of any reserved register bits. the host should not write to these bits and should add 0 for any such bit, while calculating checksum. checksum_flash_xxx regi sters (in the operat ing mode) indicate the checksum stored in the flas h. checksum_ram_xxx registers (in the operating mode) indicate the checksum calculated by the device and stored in the ram. 9. wait for 55 ms. 10.read the checksum matched bi t in the host_mode register (in the device configuration mode) and verify that it is set to 1. if this bit is not set, start again from the first step and recon- figure the device. the host should keep a backup of the configuration data if this is needed. checksum matched bit : the cy8cmbr2110 calculates the checksum and compares that wit h the checksum register value entered by the host. if both t he values match, the checksum matched bit in the host_mode register (in the device configu- ration mode) is set to 1. if the values do not match (indicating a possible i 2 c write error) this bit is cleared to 0. the host can read the checksum_ram_xxx register (in the operating mode) to know the device calculated checksum. 11.if the checksum matched bit is set to 1, then set the save to flash bit in the ho st_mode register. save to flash bit: on a save to flash, the following sequence is executed: the device copies the 64-byte data (led configuration mode and device configuration mode) to the flash. a software reset is done. after software reset, the device is in operating mode. any configuration changes are not applicable unless a save to flash is done, which is useful when the device has to be configured only once for all future operations. to ensure a flawless save to flash, the device power supply must be stable, with v dd fluctuations limited to 5% of the v dd . 12.after a save to flash, wait for (t save_flash + device initial- ization) time. t save_flash is mentioned in the flash write time specifications. the device initialization time is 350 ms (normal noise immunity) or 1000 ms (high noise immunity). 13.read the factory defaults loaded bit in device_stat register (in operating mode). factory defaults loaded bit: after every reset, the device loads the ram with the flash content and verifies the ram checksum with the flash checksum to ensure there is no flash corruption. if the checksum differs, then the device identifies it as a flash corruption and loads the factory default value in the ram, and sets the factory defaults loaded bit. this resets any register value previously changed by the host. factory default values of each register are mentio ned in the register map. if the factory defaults are loaded, the i 2 c address of the device also changes from the current addr ess (set by the host) to the default address, 37h. the host must then check for the default i 2 c address on the i 2 c bus to communicate with the cy8cmbr2110. 14.setting the factory defaults loaded bit corrupts the flash and the host needs to reconfigure the device from the first step. if this bit is clear, then the de vice is successfully configured. cy8cmbr2110 reset you can reset the cy8cmbr2110 either through hardware or software using the following options: hardware reset: for this option, toggle power on the cy8cmbr2110 pins. there are two types of hardware reset: ? power reset ? turn off the external power supply on the device v dd line and turn on again (after power down, ensure that the v dd is less than 100 mv, before powering backup). on a power reset, there is a high-going pulse of 16 ms on the hostcontrolgpo1 pin. ? xres reset ? pull the device xres pin high and then pull low. on an xres reset, there is no pulse on hostcontrolgpo1 pin. in all other respects, xres reset is identical to power reset. on a hardware reset, the led configuration mode and device configuration mode register valu es are loaded from the flash to the ram. all the device blocks are initialized, system diagnostics is done, and an initial 5-ms pulse is sent on all the gpox associated with any failing csx. this is done within 350 ms (normal noise immunity) or 1000 ms (high noise immunity). power-on led effects (if enabled) are then seen on all the remaining gpos. after this, the device is in the operating mode and normal operation begins. software reset: this is done by writing 1 to the software reset bit in the host_mode register (in operating mode). on a software reset, the led configuration mode and device configuration mode register va lues are loaded from the flash to the ram. the device auto-clears the software reset bit and all the device blocks are initializ ed. this is done within 350 ms (normal noise immunity) or 1000 ms (high noise immunity). after this, the device is in the operating mode and normal operation begins. system diagnostics is not done and power-on led effects do not occur. if the user has configured the device for power-on led effects and saved the settings to flash, a hardware reset must be done to see the power-on led effects.
cy8cmbr2110 document number: 001-74494 rev. *a page 24 of 68 layout guidelines and best practices table 8. layout guidelines and best practices sl. no. category min max recommendations/remarks 1 button shape ? ? solid round pattern, round with led hole, rectangle with round corners 2 button size 5 mm 15 mm refer to the design toolbox 3 button-button spacing equal to button ground clearance ? 8 mm (y dimension in figure 39 on page 25 ) 4 button ground clearance 0.5 mm 2 mm refer to the design toolbox (x dimension in figure 39 on page 25 ) 5 ground flood - top layer ? ? hatched ground 7 mil trace and 45 mil grid (15% filling) 6 ground flood - bottom layer ? ? hatched ground 7 mil trace and 70 mil grid (10% filling) 7 trace length from button pad to capsense controller pins ? 450 mm refer to the design toolbox 8 trace width 0.17 mm 0.20 mm 0.17 mm (7 mil) 9 trace routing ? ? traces should be routed on the non-button side. if any non-capsense trace crosses capsense trace, ensure that intersection is orthogonal. 10 via position for the buttons ? ? via should be placed near the edge of the button to reduce trace length thereby increasing sensitivity 11 via hole size for button traces ? ? 10 mil 12 no. of via on button trace 1 2 1 13 distance of capsense series resistor from button pin ? 10 mm place capsense series resistors close to the device for noise suppression. place capsense resistors, which have highest priority, first. 14 distance between any capsense trace to ground flood 10 mil 20 mil 20 mil 15 device placement ? ? mount the device on the layer opposite to button. the capsense trace length between the device and buttons should be minimum (see trace length above) 16 placement of components in two layer pcb ? ? top layer ? buttons bottom layer ? device, other components and traces. 17 placement of components in four layer pcb ? ? top layer ? buttons second layer ? capsense traces and v dd (avoid v dd traces below the buttons) third layer ? hatched ground bottom layer ? capsense controller, other components and non capsense traces 18 overlay thickness 0 mm 5 mm refer to the design toolbox 19 overlay material ? ? should be non-conductive material. glass, abs plastic, formica, wood and so on. there should be no air gap between pcb and overlay. use adhesive to stick the pcb and overlay. 20 overlay adhesives ? ? adhesive should be non conductive and dielectrically homogenous. 467mp and 468mp adhesives made by 3m are recommended. 21 led back lighting ? ? cut a hole in t he button pad and use rear mountable leds. refer to the pcb layout in the following section. 22 board thickness ? ? standard board thickness for capsense fr4 based designs is 1.6 mm.
cy8cmbr2110 document number: 001-74494 rev. *a page 25 of 68 capsense button shapes figure 38. capsense button shapes button layout design figure 39. button layout design x: button to ground clearance (refer to layout guidelines and best practices on page 24 ) y: button to button clearance (refer to layout guidelines and best practices on page 24 ) recommended via-hole placement figure 40. recommended via-hole placement
cy8cmbr2110 document number: 001-74494 rev. *a page 26 of 68 example pcb layout design with ten capsense buttons and ten leds figure 41. top layer figure 42. bottom layer capsense csx leds buzzerout1 driving led hostcontrolgpos driving leds capsense traces resistors gnd led traces v dd trace cy8cmbr2110 led ac 1-pin buzzer i 2 c header
cy8cmbr2110 document number: 001-74494 rev. *a page 27 of 68 electrical specifications this section presents the dc and ac electrical specifications of t he cy8cmbr2110 device. absolute maximum ratings exceeding maximum ratings may short en the useful life of the device. operating temperature table 9. absolute maximum ratings parameter description min typ max unit conditions t stg storage temperature ?55 +25 +125 c higher storage temperatures reduce data retention time. recommended storage temperature is +25 c 25 c. extended duration storage at temperatures above 85 c degrades reliability. v dd supply voltage relative to v ss ?0.5 ? +6.0 v v io dc voltage on capsense inputs and digital output pins v ss ? 0.5 ? v dd + 0.5 v i mig maximum current into any gpo pin ?25 ? +50 ma esd electrostatic discharge voltage 2000 ? ? v human body model esd lu latch-up current ? ? 200 ma in accordance with jesd78 standard table 10. operating temperature parameter description min typ max unit notes t a ambient temperature ?40 ? +85 c t c commercial temperature 0 ? +70 c t j operational die temper- ature ?40 ? +100 c the temperature rise from ambient to junction is package specific. refer to table 21 on page 33 . the user must limit the power consumption to comply with this requirement.
cy8cmbr2110 document number: 001-74494 rev. *a page 28 of 68 dc electrical characteristics dc chip level specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. dc general purpose i/o specifications these tables list guaranteed maximum and mi nimum specifications for the voltage and te mperature ranges: 3.0 v to 5.5 v and ?40 c t a 85c, 2.4 v to 3.0 v and ?40 c t a 85 c, or 1.71 v to 2.4 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 11. dc chip-level specifications parameter description min typ max unit notes v dd [1],[2],[3] supply voltage 1.71 ? 5.5 v i dd supply current ? 3.4 4.0 ma v dd = 3.0 v, t a = 25 c i da active current ? 3.4 4.0 ma v dd = 3.0 v, t a = 25 c, continuous button scan i ds deep sleep current ? 0.1 1.05 av dd = 3.0 v, t a = 25 c i dl low power sleep current ? 9.52 14.20 av dd = 3.0 v, t a = 25 c i av1 average current ? 90.5 ? a 4 buttons used, 180 button touches per hour, average button touch time of 1000 ms, buzzer disabled, button touch led effects disabled, 10 pf < c p of all buttons < 20 pf, button scan rate = 541 ms, with power consumption optimized, normal noise immunity level, medium csx sensitivity i av2 average current ? 111.2 ? a 8 buttons used, 200 button touches per hour, average button touch time of 500 ms, buzzer disabled, average button touch led effects time of 1000 ms, 10 pf < c p of all buttons < 20 pf, button scan rate = 541 ms, with response time optimized, normal noise immunity level, medium csx sensitivity i av3 average current ? 148.2 ? a 10 buttons used, 200 button touches per hour, average button touch time of 500 ms, buzzer disabled, average button touch led effects time of 1000 ms, 10 pf < c p of all buttons < 20 pf, button scan rate = 362 ms, with response time optimized, normal noise immunity level, medium csx sensitivity notes 8. when v dd remains in the range of 1.75 v to 1.9 v for more than 50 s, the slew rate (when moving from the 1.75 v to 1.9 v range to greater than 2 v) must be slower than 1 v/500 s. this helps to avoid tri ggering por. the only other restri ction on slew rates for any o ther voltage range or transition is the srpower_up parameter. 9. after power down, ensure that v dd falls below 100 mv before powering back up 10.for proper capsense block functionality, if the drop in v dd exceeds 5% of the base v dd , the rate at which v dd drops should not exceed 200 mv/s. base v dd can be between 1.8 v and 5.5 v. table 12. 3.0 v to 5.5 v dc general purpose i/o specifications parameter description min typ max unit notes v oh1 high output voltage on gpo0?gpo9 (except gpo5) v dd ? 0.20 ? ? v i oh 10 a, maximum of 10-ma source current in all i/os
cy8cmbr2110 document number: 001-74494 rev. *a page 29 of 68 v oh2 high output voltage on gpo0?gpo9 (except gpo5) v dd ? 0.90 ? ? v i oh = 1 ma, maximum of 20-ma source current in all i/os v oh3 high output voltage on gpo5, buzzerout0, buzzerout1, hostcontrolgpo0, hostcontrolgpo1 pins v dd ? 0.20 ? ? v i oh 10 a, maximum of 10-ma source current in all i/os v oh4 high output voltage on gpo5, buzzerout0, buzzerout1, hostcontrolgpo0, hostcontrolgpo1 pins v dd ? 0.90 ? ? v i oh = 5 ma, maximum of 20 ma source current in all i/os v ol low output voltage ? ? 0.75 v i ol = 25 ma, v dd > 3.3 v, maximum of 60-ma sink current on gpo0, gpo1 gpo2, gpo3, gpo4, buzzerout0, hostcontrolgpo0 pins and 60-ma sink current on gpo5, gpo6, gpo7, gpo8, gpo9, buzzerout1, hostcontrolgpo1 pins v il input low voltage ? ? 0.80 v v ih input high voltage 2.00 ? ? v table 13. 2.4 v to 3.0 v dc general purpose i/o specifications parameter description min typ max unit notes v oh1 high output voltage on gpo0?gpo9 (except gpo5) v dd ? 0.20 ? ? v i oh 10 a, maximum of 10-ma source current in all i/os v oh2 high output voltage on gpo0?gpo9 (except gpo5) v dd ? 0.40 ? ? v i oh = 0.2 ma, maximum of 10-ma source current in all i/os v oh3 high output voltage on gpo5, buzzerout0, buzzerout1, hostcontrolgpo0, hostcontrolgpo1 pins v dd ? 0.20 ? ? v i oh 10 a, maximum of 10-ma source current in all i/os v oh4 high output voltage on gpo5, buzzerout0, buzzerout1, hostcontrolgpo0, hostcontrolgpo1 pins v dd ? 0.50 ? ? v i oh = 2 ma, maximum of 10-ma source current in all i/os v ol low output voltage ? ? 0.75 v i ol = 10 ma, maximum of 30-ma sink current on gpo0, gpo1 gpo2, gpo3, gpo4, buzzerout0, hostcontrolgpo0 pins and 30 ma sink current on gpo5, gpo6, gpo7, gpo8, gpo9, buzzerout1, host controlgpo1 pins v il input low voltage ? ? 0.72 v v ih input high voltage 1.40 ? ? v table 12. 3.0 v to 5.5 v dc general purpose i/o specifications (continued) parameter description min typ max unit notes
cy8cmbr2110 document number: 001-74494 rev. *a page 30 of 68 dc i 2 c specifications this table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 v to 5.5 v and ?40 c t a 85c, 2.4 v to 3.0 v and ?40 c t a 85 c, & 1.71 v to 2.4 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 14. 1.71 v to 2.4 v dc general purpose i/o specifications parameter description min typ max unit notes v oh1 high output voltage on gpo0?gpo9 (except gpo5) v dd ? 0.20 ? ? v i oh = 10 a, maximum of 10-ma source current in all i/os v oh2 high output voltage on gpo0?gpo9 (except gpo5) v dd ? 0.50 ? ? v i oh = 0.5 ma, maximum of 10-ma source current in all i/os v oh3 high output voltage on gpo5, buzzerout0, buzzerout1, hostcontrolgpo0, hostcontrolgpo1 pins v dd ? 0.20 ? ? v i oh = 100 a, maximum of 10-ma source current in all i/os v oh4 high output voltage on gpo5, buzzerout0, buzzerout1, hostcontrolgpo0, hostcontrolgpo1 pins v dd ? 0.50 ? ? v i oh = 2 ma, maximum of 10-ma source current in all i/os v ol low output voltage ? ? 0.4 v i ol = 5 ma, maximum of 30-ma sink current on gpo0, gpo1 gpo2, gpo3, gpo4, buzzerout0, hostcontrolgpo0 pins and 20 ma sink current on gpo5, gpo6, gpo7, gpo8, gpo9, buzzerout1, hostcontrolgpo1 pins v il input low voltage ? ? 0.3 x v dd v v ih input high voltage 0.65 x v dd ?? v table 15. 3.0 v to 5.5 v dc general purpose io specifications symbol description min typ max unit notes v ili2c input low level ? ? 0.25 x v dd v 3.1 v v dd 5.5 v ? ? 0.3 x v dd v 2.5 v v dd 3.0 v ? ? 0.3 x v dd v1.71 v v dd 2.4 v v ihi2c input high level 0.65 v dd ??v1.71 v v dd 5.5 v
cy8cmbr2110 document number: 001-74494 rev. *a page 31 of 68 ac electrical specifications ac chip-level specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. ac general purpose i/o specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. flash write time specifications unless otherwise specified in the following ta ble, all limits guaranteed for vdd = 5.0 v. table 16. ac chip-level specifications parameter description min max unit notes sr power_up power supply slew rate - 250 v/ms v dd slew rate during power up. t xrst external reset pulse width at power-up 1 ms applicable after device power supply is active t xrst2 external reset pulse width after power-up 10 s applicable after device v dd has reached max value table 17. ac general purpose i/o specifications parameter description min typ max unit notes t rise1 rise time, strong mode on gpo0?gpo9 (except gpo5), cload = 50 pf 15 ? 80 ns v dd = 3.0 to 3.6 v, 10% to 90% t rise2 rise time, strong mode on gpo5, buzzerout0, buzzerout1, hostcontrolgpo0, hostcontrolgpo1 pins, cload = 50 pf 10 ? 50 ns v dd = 3.0 to 3.6 v, 10% to 90% t rise3 rise time, strong mode low supply on gpo0?gpo9 (except gpo5), cload = 50 pf 15 ? 80 ns v dd = 1.71 to 3.0 v, 10% to 90% t rise4 rise time, strong mode low supply on gpo5, buzzerout0, buzzerout1, hostcontrolgpo0, hostcontrolgpo1 pins, cload = 50 pf 10 ? 80 ns v dd = 1.71 to 3.0 v, 10% to 90% t fall1 fall time, strong mode, cload = 50 pf on all gpos, buzzerout pins, hostcon- trolgpo pins 10 ? 50 ns v dd = 3.0 to 3.6 v, 90% to 10% t fall2 fall time, strong mode low supply, cload = 50 pf on all gpos, buzzerout pins, hostcontrolgpo pins 10 ? 70 ns v dd = 1.71 to 3.0 v, 90% to 10% table 18. flash write time specifications parameter description min typ max unit notes t save_flash1 time taken to write to flash ? 45 120 ms t a = 0 c?100 c t save_flash2 time taken to write to flash ? 70 240 ms t a = ?40?c - 0 c
cy8cmbr2110 document number: 001-74494 rev. *a page 32 of 68 capsense specifications i 2 c specifications figure 43. definition of timing on the i 2 c bus s ? start condition p ? stop condition note 11. the max value of parasitic capacitance is 40 pf w hen the temperature is above 0 c, and 38 pf at ?45 c. table 19. capsense specifications parameter description min max unit notes c p parasitic capacitance 5.0 (c p +c f )<40 [11] pf c p is the total capacitance seen by the pin when no finger is present. c p is sum of c button , c trace , and capacitance of the vias and c pin . c f finger capacitance 0.25 (c p +c f )<40 [11] pf c f is the capacitance added by the finger touch. c pin capacitive load on pins as input 0.5 7 pf c mod external modulating capacitor 2 2.4 nf mandatory for capsense to work r s series resistor between pin and the button ? 616 ? reduces the rf noise. table 20. i 2 c specifications parameter description min max unit f scli2c scl clock frequency 0 100 khz t sustai2c setup time for a start condition 4.7 ? s t hdstai2c hold time for a start condition. after this period, the first clock pulse is generated 4.0 ? s t lowi2c low period of the scl clock 4.7 ? s t highi2c high period of the scl clock 4.0 ? s t hddati2c data hold time 0 ? s t sudati2c data setup time 250 ? ns t sustoi2c setup time for a stop condition 4.0 ? s t bufi2c bus-free time between a stop and start condition 4.7 ? s sda scl s t hdstai2c t lowi2c t highi2c t sustai2c t hddati2c t sudati2c p t sustoi2c s t bufi2c
cy8cmbr2110 document number: 001-74494 rev. *a page 33 of 68 ordering information ordering code definitions package information thermal impedance solder reflow specifications ta b l e 2 2 shows the solder reflow temperature limits that must not be exceeded. ordering code package type operating temperature capsense inputs gpo?s xres pin CY8CMBR2110-24LQXI 32 pad (5 5 0.6 mm) qfn industrial 10 10 yes CY8CMBR2110-24LQXIt 32 pad (5 5 0.6 mm) qfn (tape and reel) industrial 10 10 yes table 21. thermal impedances per package package typical ja [12] 32-pin qfn [13] 20 c/w table 22. solder reflow specifications package minimum peak temperature (t c ) maximum time above t c ? 5 c 32-pin qfn 260 ? c 30 seconds x = blank or t blank = tube; t = tape and reel temperature range: i = industrial = ?40 c to 85 c pb-free package type: lq = 32-pin qfn speed: 24 mhz part number mechanical button replacement technology code: c = cmos marketing code: 8 = psoc company id: cy = cypress c cy mbr 2110 - 24 lq 8 x x i notes 12. t j = t a + power ? ja . 13. to achieve the thermal impedance specified for the qfn package, the center thermal pad must be soldered to the pcb ground pl ane.
cy8cmbr2110 document number: 001-74494 rev. *a page 34 of 68 package diagram figure 44. cy8cmbr2110 package outline 001-42168 *d
cy8cmbr2110 document number: 001-74494 rev. *a page 35 of 68 appendix - register map 1. operating mode note 14. host access is ab:xy where: ab = read/write access for the register xy = initial value of register on device power-on for example: rw:00 = the register is both read/write accessible, with initial value 00h. r:a1 = the register is read only, with initial value a1h. #:?? = the register is reserved (no definite value stored) the shaded areas represent reserved register bits. address name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 host access [14] op,00h host_mode deep sleep software reset device_mode[2:0] rw:00 op,01h host_control_ output host control gpo3 host control gpo2 host control gpo1 host control gpo0 rw:00 op,02h reserved #:?? op,03h device_stat factory defaults loaded r:00 op,04h button_current_ stat0 cs7 status cs6 status cs5 status cs4 status cs3 status cs2 status cs1 status cs0 status r:00 op,05h button_current_ stat1 cs9 status cs8 status r:00 op,06h reserved #:?? op,07h button_latch_ stat0 cs7 latched cs6 latched cs5 latched cs4 latched cs3 latched cs2 latched cs1 latched cs0 latched r:00 op,08h button_latch_ stat1 cs9 latched cs8 latched r:00 op,09h reserved #:?? op,0ah reserved #:?? op,0bh reserved #:?? op,0ch reserved #:?? op,0dh reserved #:?? op,0eh reserved #:?? op,0fh reserved #:?? op,10h reserved #:?? op,11h reserved #:?? op,12h reserved #:?? op,13h reserved #:?? op,14h reserved #:?? op,15h reserved #:?? op,16h reserved #:?? op,17h reserved #:?? op,18h reserved #:?? op,19h reserved #:?? op,1ah cs_flash_msb checksum_flash_msb[7:0] r:00 op,1bh cs_flash_lsb checksum_flash_lsb[7:0] r:3b op,1ch cs_ram_msb checksum_ram_msb[7:0] r:00 op,1dh cs_ram_lsb checksum_ram_lsb[7:0] r:3b op,1eh device_id device_id[7:0] r:a1 op,1fh fw_rev firmware_revision[7:0] r:01
cy8cmbr2110 document number: 001-74494 rev. *a page 36 of 68 1.1 host_mode host mode register individual register names and addresses: host_mode: op, 00h this register is used to set the device into deep sleep mode, do device software reset, and set the device operation mode. to k now more about software reset, refer to cy8cmbr2110 reset on page 23 . 76543210 access: fd wc [15] : 0 wc [15] : 0 rw: 0 bit name deep sleep software reset device mode[2:0] bit name description 4 deep sleep this bit decides the device deep sleep entry and is auto-cleared by the capsense controller after the device exits from deep sleep. to know more about deep sleep, refer to power consumption and operating modes on page 20 . 0 device is in normal sleep 1 initiate deep sleep mode 3 software reset this bit resets the capsense controller 0 no impact 1 resets the capsense controller 2:0 device mode these bits decide the capsense controller?s device mode 000 operating mode 001 led configuration mode 010 device configuration mode 011 production line test mode 100 debug data mode 101 not valid 110 not valid 111 not valid note 15. device clears the write clear (wc) bit automatically after the required operation.
cy8cmbr2110 document number: 001-74494 rev. *a page 37 of 68 1.2 host_control_output host control output register individual register names and addresses: host_control_output: op, 01h this register is used to control the logic levels of the host controlled gpos. to know more, refer to host controlled gpos on page 16 . 1.3 device_stat device status register individual register names and addresses: device_stat: op, 03h this register is used to read whethe r the factory defaults or the user co nfiguration is loaded at power-up. 76543210 access: fd rw: 0 bit name host control gpo3 host control gpo2 host control gpo1 host control gpo0 bit name description 7 host control gpo3 this bit controls the logic level of the host control gpo3 0 host control gpo3 is driven logic low 1 host control gpo3 is driven logic high 6 host control gpo2 this bit controls the logic level of the host control gpo2 0 host control gpo2 is driven logic low 1 host control gpo2 is driven logic high 5 host control gpo1 this bit controls the logic level of the host control gpo1 0 host control gpo1 is driven logic low 1 host control gpo1 is driven logic high 4 host control gpo0 this bit controls the logic level of the host control gpo0 0 host control gpo0 is driven logic low 1 host control gpo0 is driven logic high 7 6 543210 access: fd r: 0 bit name factory defaults loaded bit name description 6 factory defaults loaded this bit decides whether factory de faults or the user configur ation is loaded at power up 0 user configuration is loaded at power-up of device 1 factory default configuration is loaded at power-up of device
cy8cmbr2110 document number: 001-74494 rev. *a page 38 of 68 1.4 button_current_statx capsense button current status registers individual register names and addresses: reading from these registers gives the button on/off status. 1.5 button_latch_statx capsense button latched status registers individual register names and addresses: reading from these registers gives the button latched stat us.to know more about button latched status, refer to latch status read on page 13 . button_current_stat0: op, 04h button_current_stat1: op, 05h button_current_ stat0 76543210 access: fd r: 0 r: 0 r: 0 r: 0 r: 0 r: 0 r: 0 r: 0 bit name cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 button_current_ stat1 76543210 access: fd r: 0 r: 0 bit name cs9 cs8 bit name description x csx this bit gives the button on/off status 0 button off 1 button on button_latch_stat0: op, 07h button_latch_stat1: op, 08h button_latch_ stat0 76543210 access: fd r: 0 r: 0 r: 0 r: 0 r: 0 r: 0 r: 0 r: 0 bit name cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 button_latch_ stat1 76543210 access: fd r: 0 r: 0 bit name cs9 cs8
cy8cmbr2110 document number: 001-74494 rev. *a page 39 of 68 1.6 checksum_flash_xxx flash settings checksum registers individual register names and addresses: reading 2 bytes from registers 1ah, 1bh give s the checksum of settings st ored in the flash. checksum is the sum of all the regi sters stored in flash for the device configuration (reg 0x01-0x1d) and led configuration modes (reg 0x01-0x1f). after the settings ar e saved to flash, the default settings change to the new value stored in flash. 1.7 checksum_ram_xxx ram settings checksum registers individual register names and addresses: reading 2 bytes from registers 1ch, 1dh give s the checksum of settings stored in the ra m. checksum is the sum of all the regist ers in ram for the device configuration (reg 0x01-0x 1d) and led configuration (reg 0x01-0x1f) modes. checksum_flash_msb: op, iah checksum_flash_lsb: op, 1bh checksum_flash _msb 76543210 access: fd r: 00 bit name checksum_flash_msb[7:0] checksum_flash _lsb 76543210 access: fd r: 3bh bit name checksum_flash_lsb[7:0] checksum_ram_msb: op, 1ch checksum_ram_lsb: op, 1dh checksum_ram_msb 7 6 5 4 3 2 1 0 access: fd r: 00 bit name checksum_ram_msb[7:0] checksum_ram_lsb 7 6 5 4 3 2 1 0 access: fd r: 3bh bit name checksum_ram_lsb[7:0]
cy8cmbr2110 document number: 001-74494 rev. *a page 40 of 68 1.8 device_id device identity register individual register names and addresses: device_id: op, 1eh reading 1 byte from this register gives the unique device id th rough which the device can be identified. device id for this dev ice is ?0xa1?. 1.9 fw_rev firmware revision register individual register names and addresses: fw_rev: op, 1fh reading 1 byte from this register gives the firmware revision. 76543210 access: fd r: a1 bit name device id[7:0] 76543210 access: fd r: 01 bit name device id[7:0]
cy8cmbr2110 document number: 001-74494 rev. *a page 41 of 68 2. led conf iguration mode address name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 host access [16] lc,00h host_mode device_mode[2:0] rw:01 lc,01h led_config last button led effect enable analog voltage output enable standby mode led brightness [5:4] led on time enable button touch led effects enable power on led effects enable power on led effect sequence rw:00 lc,02h led_fad_ period1 period[7:0] rw:00 lc,03h led_fad_ period2 period[7:0] rw:00 lc,04h led_fad_ period3 period[7:0] rw:00 lc,05h led_fad_ period4 period[7:0] rw:00 lc,06h gpo000_led_dim_ config1 ramp_up_time[7:6] high_brightness[5:3] led_scenario_repeat[2:0] rw:00 lc,07h gpo000_led_dim_ config2 ramp_down_time[7:6] low_brightness[5:3] breathing effect high_time low_time rw:00 lc,08h gpo123_led_dim_ config1 ramp_up_time[7:6] high_brightness[5:3] led_scenario_repeat[2:0] rw:00 lc,09h gpo123_led_dim_ config2 ramp_down_time[7:6] low_brightness[5:3] breathing effect high_time low_time rw:00 lc,0ah gpo456_led_dim_ config1 ramp_up_time[7:6] high_brightness[5:3] led_scenario_repeat[2:0] rw:00 lc,0bh gpo456_led_dim_ config2 ramp_down_time[7:6] low_brightness[5:3] breathing effect high_time low_time rw:00 lc,0ch gpo789_led_dim_ config1 ramp_up_time[7:6] high_brightness[5:3] led_scenario_repeat[2:0] rw:00 lc,0dh gpo789_led_dim_ config2 ramp_down_time[7:6] low_brightness[5:3] breathing effect high_time low_time rw:00 lc,0eh reserved #:?? lc,0fh reserved #:?? lc,10h reserved #:?? lc,11h reserved #:?? lc,12h gpo000_pwron_ led_dim_config1 ramp_up_time[7:6] high_brightness[5:3] led_scenario_repeat[2:0] rw:00 lc,13h gpo000_pwron_ led_dim_config2 ramp_down_time[7:6] low_brightness[5:3] high_time[2:1] low_time rw:00 lc,14h gpo123_pwron_ led_dim_config1 ramp_up_time[7:6] high_brightness[5:3] led_scenario_repeat[2:0] rw:00 lc,15h gpo123_pwron_ led_dim_config2 ramp_down_time[7:6] low_brightness[5:3] high_time[2:1] low_time rw:00 lc,16h gpo456_pwron_ led_dim_config1 ramp_up_time[7:6] high_brightness[5:3] led_scenario_repeat[2:0] rw:00 lc,17h gpo456_pwron_ led_dim_config2 ramp_down_time[7:6] low_brightness[5:3] high_time[2:1] low_time rw:00 lc,18h gpo789_pwron_ led_dim_config1 ramp_up_time[7:6] high_brightness[5:3] led_scenario_repeat[2:0] rw:00 lc,19h gpo789_pwron_ led_dim_config2 ramp_down_time[7:6] low_brightness[5:3] high_time[2:1] low_time rw:00 lc,1ah reserved #:?? lc,1bh reserved #:?? lc,1ch reserved #:?? lc,1dh reserved #:?? lc,1eh reserved #:?? lc,1fh reserved #:?? note 16. host access is ab:xy where: ab = read/write access for the register xy = initial value of register on device power-on for example: rw:00 = the register is both read/write accessible, with initial value 00h. r:a1 = the register is read only, with initial value a1h. #:?? = the register is reserved (no definite value stored) the shaded areas represent reserved register bits.
cy8cmbr2110 document number: 001-74494 rev. *a page 42 of 68 2.1 host_mode host mode register individual register names and addresses: host_mode: lc, 00h this register is used to set the device operation mode. 2.2 led_config led effects configuration register individual register names and addresses: led_config: lc, 01h this register is used to enable/disable button touch led effects and power-on led effects , and decides the power-on led effect sequence, led on time enable/disable, sets the standby mode led brightness , analog voltage output enable/disable, and last button led effect enable/disable. 76543210 access: fd rw: 1 bit name device mode[2:0] bit name description 2:0 device mode these bits decide the capsense controller device mode 000 operating mode 001 led configuration mode 010 device configuration mode 011 production line test mode 100 debug data mode 101 not valid 110 not valid 111 not valid 76543 210 access: fd rw: 0 rw: 0 rw: 0 rw: 0 rw: 0 rw: 0 rw: 0 bit name last button led effect enable analog voltage output enable standby mode led brightness[5:4] led on time enable button touch led effects enable power on led effects enable power on led effects sequence
cy8cmbr2110 document number: 001-74494 rev. *a page 43 of 68 bit name description 7 last button led effect enable this bit decides whether led effects should continue on all the gpos or only on the last button touched 0 led effects on any button touched based on the settings 1 led effects only on the last button touched 6 analog voltage output enable this bit decides whether output pins can be used as open drain switches 0 output pins cannot be us ed for analog output voltage 1 output pins can be used for analog output voltage 5:4 standby mode led brightness these bits set the standby mode led brightness 3 led on time enable this bit enables the led on time after button is released 0 led on time disabled 1 led on time enabled and led on time value is taken from the led_fad_period1 register. 2 button touch led effects enable this bit enables or disables the button touch led effects. if this bit is not set, settings from register 0x06 ? 0x0d are ignored. 0 disable the button touch led effects 1 enable the button touch led effects 1 power on led effects enable this bit enables or disables the power-on led ef fects. if this bit is not set, settings from register 0x12 ? 0x19 are ignored. 0 disable the power-on led effects 1 enable the power-on led effects 0 power on led effect sequence this bit decides the power-on led effects sequence on gpos. 0 power on led effects on all gpos appear concurrently 1 power on led effects on all gpos appear sequentially. the sequence is gpo0>gpo1>.....gpo9 standby mode led brightness bits led brightness 0b00 0% 0b01 20% 0b10 30% 0b11 50%
cy8cmbr2110 document number: 001-74494 rev. *a page 44 of 68 2.3 led_fad_periodx led effects global timing registers individual register names and addresses: this register is used to set t he led effect timings. each step increment in this register corresponds to increment of 20 ms in the led effect timings. 2.4 gpoxxx_led_dim_config1 led effects configuration registers individual register names and addresses: this register is used to set the ramp up time, high brightne ss intensity, and the led scenario repeat rate for the led effects. the following table gives the list of registers and the corresponding gpos whose led effects are controlled by the register setting s. led_fad_period1: lc, 02h l ed_fad_period2: lc, 03h led_fad_period3: lc, 04h l ed_fad_period4: lc, 05h 76543210 access: fd rw: 00 bit name period[7:0] gpo000_led_dim_config1:lc,06h gpo123_led_dim_c onfig1:lc,08h gpo456_led _dim_config1:lc,0ah gpo789_led_dim_config1:lc,0ch 765432 1 0 access: fd rw:00 rw: 00 rw: 00 bit name t ru [7:6] high_brightness[5:3] led_scenario_repeat[2:0] register name gpos with defined e ffect in the register gpo000_led_dim_config1 gpo0 gpo123_led_dim_config 1 gpo1, gpo2, gpo3 gpo456_led_dim_config 1 gpo4, gpo5, gpo6 gpo789_led_dim_config 1 gpo7, gpo8, gpo9
cy8cmbr2110 document number: 001-74494 rev. *a page 45 of 68 bit name description 7:6 t ru [7:6] these bits decide the global setting time that will be used as ramp up time 5:3 high_brightness[5:3] these bits decide what should be the hi gh brightness state intensity 2:0 led_scenario_repeat[2:0] these bits decide how many times the led effects should be repeated after the corresponding button is released. t ru [7:6] ramp up time 0b00 led_fad_period1 0b01 led_fad_period2 0b10 led_fad_period3 0b11 led_fad_period4 high_brightness[5:3] ramp up target intensity 0b000 100% 0b001 90% 0b010 80% 0b011 65% 0b100 50% 0b101 40% 0b110 20% 0b111 0% led_scenario_repeat[2:0] led scenario repeat rate 0b000 0 0b001 1 0b010 2 0b011 4 0b100 6 0b101 10 0b110 15 0b111 20
cy8cmbr2110 document number: 001-74494 rev. *a page 46 of 68 2.5 gpoxxx_led_dim_config2 led effects configuration registers individual register names and addresses: these registers are used to set the ramp down time, low brig htness intensity, the high brightness time, and the low brightness time for the led effects. these registers also control the led breath ing effect. the following table gives information about which g po?s led effects are controlled by which register settings. gpo000_led_dim_config2:lc, 07h gpo123_led_dim_c onfig2:lc,09h gpo456_led _dim_config2:lc,0bh gpo789_led_dim_config2:lc,0dh 76543210 access: fd rw: 00 rw: 00 rw: 0 rw: 0 rw: 0 bit name t rd [7:6] low_brightness[5:3] breathing effect t h t l register name gpos with defined effect in the register gpo000_led_dim_config2 gpo0 gpo123_led_dim_config2 gpo1, gpo2, gpo3 gpo456_led_dim_config2 gpo4, gpo5, gpo6 gpo789_led_dim_config2 gpo7, gpo8, gpo9 bit name description 7:6 t rd [7:6] these bits decide the global setting time that will be used as ramp down time 5:3 low_brightness[5: 3] these bits decide what should be the low bri ghtness state intensity 2 breathing effect this bit decides whether led effe cts should be repeated while the button is kept touched 0 led effects are not repeat ed while the button is kept touched 1 led effects are repeated while the button is kept touched t rd [7:6] ramp down time 0b00 led_fad_period1 0b01 led_fad_period2 0b10 led_fad_period3 0b11 led_fad_period4 low_brightness[5:3] ramp down target intensity 0b000 0% 0b001 10% 0b010 20% 0b011 30% 0b100 40% 0b101 60% 0b110 80% 0b111 100%
cy8cmbr2110 document number: 001-74494 rev. *a page 47 of 68 2.6 gpoxxx_pwron_led_dim_config1 power-on led effects configuration registers individual register names and addresses: these registers are used to set the ramp up time, high brightne ss intensity and the led scenario repeat rate for power-on led e ffects. the following table gives information about what gpo?s power- on led effects are controlled by which register settings. 1t h this bit decides the global setting time that will be used as high brightness time. 0t l this bit decides the global setting time that will be used as low brightness time. gpo000_pwron_led_dim_config1:lc, 12 h gpo123_pwron_led_dim_config1:lc, 14h gpo456_pwron_led_dim_config1:lc, 16 h gpo789_pwron_led_dim_config1:lc, 18h 765432 1 0 access: fd rw: 00 rw: 00 rw: 00 bit name t ru [7:6] high_brightness[5:3] led_scenario_repeat[2:0] register name gpos with defined effect in the register gpo000_pwron_led_dim_config1 gpo0 gpo123_pwron_led_dim_co nfig1 gpo1, gpo2, gpo3 gpo456_pwron_led_dim_co nfig1 gpo4, gpo5, gpo6 gpo789_pwron_led_dim_co nfig1 gpo7, gpo8, gpo9 bit name description 7:6 t ru [7:6] these bits decide the global setting time that will be used as ramp up time. bit name description t h high brightness time 0 led_fad_period1 1 led_fad_period2 t l low brightness time 0 led_fad_period1 1 led_fad_period2 t ru [7:6] ramp up time 0b00 led_fad_period1 0b01 led_fad_period2 0b10 led_fad_period3 0b11 led_fad_period4
cy8cmbr2110 document number: 001-74494 rev. *a page 48 of 68 2.7 gpoxxx_pwron_led_dim_config2 power on led effects configuration registers individual register names and addresses: these registers are used to set the ramp down time, low brig htness intensity, the high brightness time, and the low brightness time in the power-on led effect architecture. the following table give s information of what gpo?s power-on led effects are controlle d by which register settings. 5:3 high_brightness[5:3] these bits decide what s hould be the high brightness state intensity. 2:0 led_scenario_repeat[2:0] these bits decide on how many times the power-on led effects should be re- peated. gpo000_pwron_led_dim_config2:lc, 13 h gpo123_pwron_led_dim_config2:lc, 15h gpo456_pwron_led_dim_config2:lc, 17 h gpo789_pwron_led_dim_config2:lc, 19h 765 4 3 2 1 0 access: fd rw: 00 rw: 00 rw: 00 rw: 0 bit name t rd [7:6] low_brightness[5:3] t h [2:1] t l register name gpos with defined effect in the register gpo000_pwron_led_dim_config2 gpo0 gpo123_pwron_led_dim_co nfig2 gpo1, gpo2, gpo3 gpo456_pwron_led_dim_co nfig2 gpo4, gpo5, gpo6 gpo789_pwron_led_dim_co nfig2 gpo7, gpo8, gpo9 bit name description high_brightness[5:3] ramp up target intensity 0b000 100% 0b001 90% 0b010 80% 0b011 65% 0b100 50% 0b101 40% 0b110 20% 0b111 0% led_scenario_repeat[2:0] led scenario repeat rate 0b000 0 0b001 1 0b010 2 0b011 4 0b100 6 0b101 10 0b110 15 0b111 20
cy8cmbr2110 document number: 001-74494 rev. *a page 49 of 68 bit name description 7:6 t rd [7:6] these bits decide which global setting time is used as ramp down time. 5:3 low_brightness[5:3] these bits deci de the low-brightness state intensity. 2:1 t h [2:1] these bits decide which global setting time is used as high-brightness time. 0t l this bit decides which global setting time is used as low-brightness time. t rd [7:6] ramp down time 0b00 led_fad_period1 0b01 led_fad_period2 0b10 led_fad_period3 0b11 led_fad_period4 low_brightness[5:3] ramp down target intensity 0b000 0% 0b001 10% 0b010 20% 0b011 30% 0b100 40% 0b101 60% 0b110 80% 0b111 100% t h [2:1] high brightness time 0b00 led_fad_period1 0b01 led_fad_period2 0b10 led_fad_period3 0b11 led_fad_period4 t l low brightness time 0 led_fad_period1 1 led_fad_period2
cy8cmbr2110 document number: 001-74494 rev. *a page 50 of 68 3. device c onfiguration mode address name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 host access [17] dc,00h host_mode load factory defaults checksum matched save to flash device_mode[2:0] rw:12 dc,01h i2c_cfg i2c_address[6:0] rw:37 dc,02h dev_features auto_reset[4:3] automatic threshold emc rw:02 dc,03h fss_group0 cs7_fss cs6_fss cs5_fss cs4_fss cs3_fss cs2_fss cs1_fss cs0_fss rw:00 dc,04h fss_group1 cs9_fss cs8_fss rw:00 dc,05h reserved #:?? dc,06h toggle0 cs7_toggle cs6_toggle cs5_toggle cs4_toggle cs3_toggle cs2_toggl e cs1_toggle cs0_toggle rw:00 dc,07h toggle1 cs9_toggle cs8_toggle rw:00 dc,08h reserved #:?? dc,09h sensitivity0 cs3_sensitivity cs2_sensit ivity cs1_sensitivity cs0_sensitivity rw:00 dc,0ah sensitivity1 cs7_sensitivity cs6_sensit ivity cs5_sensitivity cs4_sensitivity rw:00 dc,0bh sensitivity2 cs9_sensitivity cs8_sensitivity rw:00 dc,0ch reserved #:?? dc,0dh reserved #:?? dc,0eh cs0_deb cs0_debounce[7:0] rw:01 dc,0fh cs1-cs9_deb cs1-cs9_debounce[7:0] rw:01 dc,10h reserved #:?? dc,11h finger_threshold0 cs1_finger_threshold[7:4] cs0_finger_threshold[3:0] rw:00 dc,12h finger_threshold1 cs3_finger_threshold[7:4] cs2_finger_threshold[3:0] rw:00 dc,13h finger_threshold2 cs5_finger_threshold[7:4] cs4_finger_threshold[3:0] rw:00 dc,14h finger_threshold3 cs7_finger_threshold[7:4] cs6_finger_threshold[3:0] rw:00 dc,15h finger_threshold4 cs9_finger_threshold[7:4] cs8_finger_threshold[3:0] rw:00 dc,16h reserved #:?? dc,17h reserved #:?? dc,18h reserved #:?? dc,19h reserved #:?? dc,1ah scanrate power consumption optimized scanrate[6:0] rw:00 dc,1bh buzzer_config buzzer_enable pins pin0 idle state frequency[2:0] rw:00 dc,1ch buz_op_duration buzzerdelay_value[6:0] rw:00 dc,1dh custom_cfg1 customer_check_data[7:0] rw:00 dc,1eh checksum_msb checksum_msb[7:0] rw:00 dc,1fh checksum_lsb checksum_lsb[7:0] rw:3b note 17. host access is ab:xy where: ab = read/write access for the register xy = initial value of register on device power-on for example: rw:00 = the register is both read/write accessible, with initial value 00h. r:a1 = the register is read only, with initial value a1h. #:?? = the register is reserved (no definite value stored) the shaded areas represent reserved register bits
cy8cmbr2110 document number: 001-74494 rev. *a page 51 of 68 3.1 host_mode host mode register individual register names and addresses: host_mode: dc, 00h this register is used to save the configuration to flash, dec ide the device operation mode, and load factory defaults. this reg ister also tells whether the checksum is matched; to know more about checksum match, refer to steps to configure cy8cmbr2110 on page 23 . 765 4 3210 access: fd wc [18] : 0 r: 1 wc [18] : 0 rw: 2 bit name load factory defaults checksum matched save to flash device mode[2:0] bit name description 5 load factory defaults this bit is used to load factory default setting in ram. however user configured flash area does not get updated with these settings 0 no impact 1 load factory defaults and bit is self cleared after loading factory defaults 4 checksum matched this bit is set or cleared based on the host sent checksum and the checksum calculated with the register data of device conf iguration mode and led configuration mode 0 host sent checksum a nd checksum calculated did not match 1 host sent checksum and checksum calculated matched 3 save to flash this bit is used to stor e the current configuration into flash 0 no impact 1 stores the current configuration into flash 2:0 device mode these bits decide the capsense controller device mode 000 operating mode 001 led configuration mode 010 device configuration mode 011 production line test mode 100 debug data mode 101 not valid 110 not valid 111 not valid note 18. device clears the write clear (wc) bit automatically after the required operation.
cy8cmbr2110 document number: 001-74494 rev. *a page 52 of 68 3.2 i2c_cfg i 2 c configuration register individual register names and addresses: i2c_cfg: dc, 01h this register is used to set the i 2 c slave address. slave address range is 0x00-0x7f. 3.3 dev_features device features configuration register individual register names and addresses: dev_features: dc, 02h this register is used to enable/disable automatic thresholds and noise immunity level, and set the button auto reset period. 76543210 access: fd rw: 37 bit name i2c_address[6:0] bit name description 6:0 i2c_address[6:0] these bits set the 7-bit i 2 c slave address 76 5 4 3 2 1 0 access: fd rw: 0 rw:1 rw:0 bit name arst_delay[4:3] automatic threshold emc bit name description 3:2 arst[3:2] these bits decide button auto reset period. 1 automatic threshold this bit decides whether all thresholds are automatica lly calculated (automatic threshold enabled) or if the user should give finger th reshold input and all other thresholds are calcu- lated based on the finger threshold by the capsense controller 0 disables automatic threshold calculation in smartsense auto-tuning 1 enables automatic threshold calculation in smartsense auto-tuning 0 emc this bit decides the noise immunity level 0 noise immunity level is normal 1 noise immunity level is high arst[3:2] button auto reset period 0b00 no limit 0b01 no limit 0b10 5 sec 0b11 20 sec
cy8cmbr2110 document number: 001-74494 rev. *a page 53 of 68 3.4 fss_groupx capsense fss group setting registers individual register names and addresses: these registers are used to set the buttons on which fss needs to be applied. 3.5 togglex toggle setting registers individual register names and addresses: this register is used to decide if the csx acts like a toggle switch. fss_group0: dc, 03h fss_group0: dc, 04h fss_group0 7 6 5 4 3 2 1 0 access: fd rw: 0 rw: 0 rw: 0 rw: 0 rw: 0 rw: 0 rw: 0 rw: 0 bit name cs7_fss cs6_fss cs5_fss cs4_fss cs3_fss cs2_fss cs1_fss cs0_fss fss_group1 7 6 5 4 3 2 1 0 access: fd rw: 0 rw: 0 bit name cs9_fss cs8_fss bit name description x csx_fss this bit decides whether the button will be in the fss group or not 0 button not in fss group 1 button in fss group toggle0: dc, 06h toggle1: dc, 07h toggle0 7 6 5 4 3 2 1 0 access: fd rw: 0 rw: 0 rw: 0 rw: 0 rw: 0 rw: 0 rw: 0 rw: 0 bit name cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 toggle1 7 6 5 4 3 2 1 0 access: fd rw: 0 rw: 0 bit name cs9 cs8 bit name description x csx_fss this bit decides whether gpox s hould be toggled based on csx status or not 0 toggle disabled 1 toggle enabled
cy8cmbr2110 document number: 001-74494 rev. *a page 54 of 68 3.6 sensitivityx capsense button sensitivity setting registers individual register names and addresses: these registers set the capsense button sensitivity. 3.7 cs0_deb cs0 debounce setting register individual register names and addresses: this register sets the cs0 debounce. range of this register is 1-255. 3.8 cs1-cs9_deb cs1 to cs9 debounce setting register individual register names and addresses: this register sets the cs1 to cs9 buttons debounce. range of this register is 1-255. sensitivity0: dc, 09h sensitivity1 : dc, 0ah sensitivity2: dc, 0bh sensitivity0 7 6 5 4 3 2 1 0 access: fd rw: 0 rw: 0 rw: 0 rw: 0 bit name cs3_sensitivity cs2_sensitivity cs1_sensitivity cs0_sensitivity sensitivity1 7 6 5 4 3 2 1 0 access: fd rw: 0 rw: 0 rw: 0 rw: 0 bit name cs7_sensitivity cs6_sensitivity cs5_sensitivity cs4_sensitivity sensitivity2 7 6 5 4 3 2 1 0 access: fd rw: 0 rw: 0 bit name cs9_sensitivity cs8_sensitivity csx_sensitivity bits button sensitivity 0b00 high sensitivity 0b01 high sensitivity 0b10 medium sensitivity 0b11 low sensitivity cs0_deb: dc, 0eh 7654321 0 access: fd rw: 01 bit name debounce [7:0] cs1-cs9_deb: dc, 0fh 765432 1 0 access: fd rw: 01 bit name debounce [7:0]
cy8cmbr2110 document number: 001-74494 rev. *a page 55 of 68 3.9 finger_thresholdx capsense button finger threshold setting registers individual register names and addresses: these registers set the finger threshold of capsense buttons finger threshold of button ?x? = 50 + (13 * csx_finger_threshold[3:0]) 3.10 scanrate scan rate settings register individual register names and addresses: this register decides the button scan rate based on the power consumption optimized bit, the number of buttons, and user config ured scan rate. based on the scan rate input selected in bits 6:0, one of the following offsets is added to the scan rate constant i n the user configured scan rate mode. 0,6,12,20,29,39,49,61,73, 86,99,114,128,144,160, 176,194,211, 229,248,26 7,287,307,327,34 8,369,391,413,43 6,459,482,506 if bit7 is set to '1' then power consumption optimization is enabled else response time optimization is enabled. finger_threshol d0:dc,11h finger_threshold1:d c,12h finger_threshold2:dc,13h finger_threshold3:dc,14h finger_threshold4:dc,15h finger_thresholdx 7 6 5 4 3 2 1 0 access: fd rw: 00 rw: 00 bit name csy_finger_threshold[7:4] csx_finger_threshold[3:0] scanrate: dc, 1ah 7 654321 0 access: fd rw:00 rw:00 bit name power consumption optimized scanrate[6:0]
cy8cmbr2110 document number: 001-74494 rev. *a page 56 of 68 3.11 buzzer_config buzzer output configuration register individual register names and addresses: buzzer_config: dc, 1bh this register is used to enable buzzer ou tput, select the number of buzzer output pins , buzzer output pins idle state logic lev el, and the buzzer output frequency 3.12 buz_op_duration buzzer output duration register individual register names and addresses: buz_op_duration: dc, 1ch the buzzer output is driven for the buzzerdelay_values[6:0] x bu tton scan rate constant. buzzerdelay_values can range from 1 to 127 if the buzzer is enabled. for th e button scan rate constant, see table 7 on page 20 . 76543210 access: fd rw: 0 rw: 0 rw: 0 rw:00 bit name en pins idle0 frequency[2:0] bit name description 6 en this bit is used to enable or disable the buzzer output 0 disable the buzzer output 1 enable the buzzer output 5 pins this bit is used to select the number of buzzer output pins 0 one buzzer output pin (ac 1-pin buzzer) 1 two buzzer output pins (ac 2-pin buzzer) 4 idle0 this bit decides the logic level of buzzerout0 in idle state 0 buzzerout0 is driven logic?0? in idle state 1 buzzerout0 is driven logic?1? in idle state 2:0 frequency[2:0] these bits decide the frequency of the buzzer output. 76543210 access: fd rw: 00 bit name buzzerdelay_values[6:0] frequency[2:0] buzzer output freq (khz) duty cycle 0b000 4.00 50% 0b001 4.00 50% 0b010 2.67 66.7% 0b011 2.00 50% 0b100 1.60 60% 0b101 1.33 50% 0b110 1.14 57.1% 0b111 1.00 50%
cy8cmbr2110 document number: 001-74494 rev. *a page 57 of 68 3.13 custom_config1 host custom data storage registers individual register names and addresses: this register can be used by customers to write their own data and save to flash. 3.14 checksum_xxx device configuration checksum registers individual register names and addresses: checksum is addition of re gister values from 0x01- 0x1f in led configuration mode , and 0x01-0x1d in the device configuration mo de. custom_config1: dc, 1dh 765432 1 0 access: fd rw: 0 bit name data[7:0] checksum_msb: dc, 1eh checksum_lsb: dc, 1fh checksum_msb 76543210 access: fd rw: 00 bit name checksum_msb[7:0] checksum_lsb 7 6 5 4 3 2 1 0 access: fd rw: 3bh bitname checksum_lsb[7:0]
cy8cmbr2110 document number: 001-74494 rev. *a page 58 of 68 4. production li ne testing mode address name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 host access [19] pl,00h host_mode host control gpo3 host control gpo2 host control gpo1 host control gpo0 device_mode[2:0] rw:03 pl,01h reserved #:?? pl,02h reserved #:?? pl,03h button_count number of working buttons detected r:00 pl,04h button_current_ stat0 cs7 status cs6 status cs5 status cs4 status cs3 status cs2 status cs1 status cs0 status r:00 pl,05h button_current_ stat1 cs9 status cs8 status r:00 pl,06h reserved #:?? pl,07h csx_short_gnd0 cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 r:00 pl,08h csx_short_gnd1 cs9 cs8 r:00 pl,09h reserved #:?? pl,0ah csx_short_csy0 cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 r:00 pl,0bh csx_short_csy1 cs9 cs8 r:00 pl,0ch reserved #:?? pl,0dh csx_cp_>40pf_0 cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 r:00 pl,0eh csx_cp_>40pf_0 cs9 cs8 r:00 pl,0fh reserved #:?? pl,10h csx_short_vdd0 cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 r:00 pl,11h csx_short_vdd1 cs9 cs8 r:00 pl,12h reserved #:?? pl,13h cmod_value c mod < 1 nf c mod > 4 nf r:00 pl,14h cs01_snr cs1_snr[3:0] cs0_snr[3:0] r:00 pl,15h cs23_snr cs3_snr[3:0] cs2_snr[3:0] r:00 pl,16h cs45_snr cs5_snr[3:0] cs4_snr[3:0] r:00 pl,17h cs67_snr cs7_snr[3:0] cs6_snr[3:0] r:00 pl,18h cs89_snr cs9_snr[3:0] cs8_snr[3:0] r:00 pl,19h reserved #:?? pl,1ah reserved #:?? pl,1bh reserved #:?? pl,1ch reserved #:?? pl,1dh reserved #:?? pl,1eh reserved #:?? pl,1fh reserved #:?? note 19. host access is ab:xy where: ab = read/write access for the register xy = initial value of register on device power-on for example: rw:00 = the register is both read/write accessible, with initial value 00h. r:a1 = the register is read only, with initial value a1h. #:?? = the register is reserved (no definite value stored) the shaded areas represent reserved register bits
cy8cmbr2110 document number: 001-74494 rev. *a page 59 of 68 4.1 host_mode host mode register individual register names and addresses: host_mode: pl, 00h this register is used to control the logic levels of the host control gpos, and decides the device operating mode. 76543210 access: fd rw: 0 rw: 0 rw: 0 rw: 0 rw: 3 bit name host control gpo3 host control gpo2 host control gpo1 host control gpo0 device mode[2:0] bit name description 7 host control gpo3 this bit controls the logic level of the host control gpo3 0 host control gpo3 is driven logic low 1 host control gpo3 is driven logic high 6 host control gpo2 this bit controls the logic level of the host control gpo2 0 host control gpo2 is driven logic low 1 host control gpo2 is driven logic high 5 host control gpo1 this bit controls the logic level of the host control gpo1 0 host control gpo1 is driven logic low 1 host control gpo1 is driven logic high 4 host control gpo0 this bit controls the logic level of the host control gpo0 0 host control gpo0 is driven logic low 1 host control gpo0 is driven logic high 2:0 device mode these bits decide the capsense controller device mode 000 operating mode 001 led configuration mode 010 device configuration mode 011 production line test mode 100 debug data mode 101 not valid 110 not valid 111 not valid
cy8cmbr2110 document number: 001-74494 rev. *a page 60 of 68 4.2 button_count detected button count register individual register names and addresses: button_count: pl, 03h this register gives information about the number of working butt ons detected. the host can read th is register and if the workin g button matches the host estimated coun t, then the system diagnostics of all buttons ha s passed. if system dia gnostics of any button fa ils, then the button is disabled. 4.3 button_current_statx capsense button current status registers individual register names and addresses: reading from these registers gives the button on/off status. 76543210 access: fd r: 0 bit name working_buttons [3:0] bit name description 3:0 working buttons these bits contain the number of working buttons detected and can be read by the host to detect whether system diagnostics passes or fails. button_current_stat0: pl, 04h button_current_stat1: pl, 05h button_current_ stat0 765432 1 0 access: fd r: 0 r: 0 r: 0 r: 0 r: 0 r: 0 r: 0 r: 0 bit name cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 button_current_ stat1 765432 1 0 access: fd r: 0 r: 0 bit name cs9 cs8 bit name description x csx this bit gives the button on/off status 0 button off 1 button on
cy8cmbr2110 document number: 001-74494 rev. *a page 61 of 68 4.4 csx_short_gndx capsense buttons short to ground information registers individual register names and addresses: this register gives information of any button that is shorted to ground. if any bit in the register is set to '1', then the cor responding button is connected to ground. capsense bu ttons do not operate when they are connecte d to ground; these buttons are disabled. 4.5 csx_short_csyz capsense buttons short to other capsense button information registers individual register names and addresses: this register gives information of any butto n that is shorted to anothe r button. if any two buttons are shorted to each other, then bits corresponding to both the buttons are set to '1 ' and the corresponding buttons are disabled. 4.6 csx_cp_>40 pf_x capsense buttons parasitic capacitance >40 pf information registers individual register names and addresses: this register gives information of buttons whose parasitic capacitance (c p ) is >40 pf. if any button c p is >40 pf, then the bit in the register is set and that button is disabled. csx_short_gnd0: pl, 07h csx_short_gnd1: pl, 08h csx_short_gnd0 7 6 5 4 3 2 1 0 access: fd r: 0 r: 0 r: 0 r: 0 r: 0 r: 0 r: 0 r: 0 bit name cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 csx_short_gnd176543210 access: fd r: 0 r: 0 bit name cs9 cs8 csx_short_csy0: pl, 0ah csx_short_csy1: pl, 0bh csx_short_csy076543210 access: fd r: 0 r: 0 r: 0 r: 0 r: 0 r: 0 r: 0 r: 0 bit name cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 csx_short_csy176 5432 1 0 access: fd r: 0 r: 0 bit name cs9 cs8 csx_cp_>40 pf_0: pl, 0dh csx_cp_>40 pf_1: pl, 0eh csx_cp_>40 pf_0 7 6 5 4 3 2 1 0 access: fd r: 0 r: 0 r: 0 r: 0 r: 0 r: 0 r: 0 r: 0 bit name cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 csx_cp_>40 pf_1 7 6 5 4 3 2 1 0 access: fd r: 0 r: 0 bit name cs9 cs8
cy8cmbr2110 document number: 001-74494 rev. *a page 62 of 68 4.7 csx_short_vddx capsense buttons short to v dd information registers individual register names and addresses: this register gives information of any button that is shorted to v dd . if any bit in the register is set to '1', then the corresponding button is connected to v dd . capsense buttons do not operate when they are connected to v dd , and are disabled. 4.8 cmod_value incorrect c mod value information registers individual register names and addresses: this register gives information if an incorrect value of c mod is connected. if the proper value of c mod is connected, then both bits ?0? and ?1? are set to ?0?. 4.9 csxy_snr capsense button snr information registers individual register names and addresses: these registers give the signal to noise ratio information of the enabled buttons. csx_short_vdd0: pl, 10h csx_short_vdd1: pl, 11h csx_short_vdd0 7 6 5 4 3 2 1 0 access: fd r: 0 r: 0 r: 0 r: 0 r: 0 r: 0 r: 0 r: 0 bit name cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 csx_short_vdd1 7 6 5 4 3 2 1 0 access: fd r: 0 r: 0 bit name cs9 cs8 cmod_value: pl, 13h 76543 2 1 0 access: fd r: 0 r: 0 bit name c mod < 1 nf c mod > 4 nf bit name description 0c mod > 4 nf this bit gives information if c mod value detected is greater than the recommended range 0 c mod is < 4 nf 1 c mod is > 4 nf 1c mod < 1 nf this bit gives information if the c mod value detected is less than the recommended range 0 c mod is > 1 nf 1 c mod is < 1 nf cs01_snr: pl, 14h cs23_snr: pl, 15h cs45_snr: pl, 16h cs67_snr: pl, 17h cs89_snr: pl, 18h 76543210 access: fd rw: 00 rw: 00 bit name csy_snr[7:4] csx_snr[3:0]
cy8cmbr2110 document number: 001-74494 rev. *a page 63 of 68 5. debug data mode note 20. host access is ab:xy where: ab = read/write access for the register xy = initial value of register on device power-on for example: rw:00 = the register is both read/write accessible, with initial value 00h. r:a1 = the register is read only, with initial value a1h. #:?? = the register is reserved (no definite value stored) the shaded areas represent reserved register bits. address name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 host access [20] dd,00h host_mode host control gpo3 host control gpo2 host control gpo1 host control gpo0 device_mode[2:0] rw:04 dd,01h button_number sensor[4:0] rw:00 dd,02h parameter parameter[4:0] rw:00 dd,03h reserved r:00 dd,04h button_current_ stat0 cs7 status cs6 status cs5 status cs4 status cs3 status cs2 status cs1 status cs0 status r:00 dd,05h button_current_ stat1 cs9 status cs8 status r:00 dd,06h reserved #:?? dd,07h read0 data[7:0] r:?? dd,08h read1 data[7:0] r:?? dd,09h read2 data[7:0] r:?? dd,0ah read3 data[7:0] r:?? dd,0bh read4 data[7:0] r:?? dd,0ch read5 data[7:0] r:?? dd,0dh read6 data[7:0] r:?? dd,0eh read7 data[7:0] r:?? dd,0fh read8 data[7:0] r:?? dd,10h read9 data[7:0] r:?? dd,11h read10 data[7:0] r:?? dd,12h read11 data[7:0] r:?? dd,13h read12 data[7:0] r:?? dd,14h read13 data[7:0] r:?? dd,15h read14 data[7:0] r:?? dd,16h read15 data[7:0] r:?? dd,17h read16 data[7:0] r:?? dd,18h read17 data[7:0] r:?? dd,19h read18 data[7:0] r:?? dd,1ah read19 data[7:0] r:?? dd,1bh read20 data[7:0] r:?? dd,1ch read21 data[7:0] r:?? dd,1dh read22 data[7:0] r:?? dd,1eh read23 data[7:0] r:?? dd,1fh read24 data[7:0] r:??
cy8cmbr2110 document number: 001-74494 rev. *a page 64 of 68 5.1 host_mode host mode register individual register names and addresses: host_mode: dd, 00h this register is used to control t he logic levels of the host control gpos, and decide the device operating mode. 76543210 access: fd rw: 0 rw: 0 rw: 0 rw: 0 rw: 4 bit name host control gpo3 host control gpo2 host control gpo1 host control gpo0 device mode[2:0] bit name description 7 host control gpo3 this bit controls the logic level of the host control gpo3 0 host control gpo3 is driven logic low 1 host control gpo3 is driven logic high 6 host control gpo2 this bit controls the logic level of the host control gpo2 0 host control gpo2 is driven logic low 1 host control gpo2 is driven logic high 5 host control gpo1 this bit controls the logic level of the host control gpo1 0 host control gpo1 is driven logic low 1 host control gpo1 is driven logic high 4 host control gpo0 this bit controls the logic level of the host control gpo0 0 host control gpo0 is driven logic low 1 host control gpo0 is driven logic high 2:0 device mode these bits decide the capsense controller device mode 000 operating mode 001 led configuration mode 010 device configuration mode 011 production line test mode 100 debug data mode 101 not valid 110 not valid 111 not valid
cy8cmbr2110 document number: 001-74494 rev. *a page 65 of 68 5.2 button_number start button number of debug data register individual register names and addresses: button_number: dd, 01h this register decides the start button number from which the dat a in registers 0x07-0x1f are fille d. for example, if the button number is selected to '4' and the parameter (register no 0x02) is select ed to raw count, then from register 0x07 raw count of buttons cs4, cs5, cs6, cs7, cs8, and cs9 are filled (assumption is all buttons are enabled). 5.3 parameter parameter of debug data register individual register names and addresses: parameter: dd, 02h this register decides the type of data that is filled from register 0x07. for example, if the button number is selected to '4' and the parameter (register no 0x02) is selected to raw count, then from register 0x07 the raw count of buttons cs4, cs5, cs6, cs7, cs8 , and cs9 are filled (the assumpti on is all buttons are enabled). for example, if the button number (registe r number 0x01) is selected to ?3? and parameter is selected to dif, then the differen ce counts of the buttons cs3, cs4, cs5, cs6, cs7, cs8, and cs9 (assuming all t he buttons are enabled) are fill ed sequentially from regist er 0x07 to 0x14 with msb filled first, followed by lsb (since dif data is of two bytes for each button). the following table shows how the registers are filled in this case. 76543210 access: fd rw: 00 bit name button[4:0] 76543210 access: fd rw: 00 bit name parameter[2:0] parameter[2:0] parameter bytes taken for each button 0c p 1 1 raw counts (rc) 2 2 difference counts (dif) 2 3 raw counts (rc), base line (bl) 2 + 2 = 4 4 all parameters of one button (rc, bl, dif, c p , snr) 2 + 2 + 2 + 1 + 1 = 8 register register name value written to register 0x07 read0 dif3_msb 0x08 read1 dif3_lsb 0x09 read2 dif4_msb 0x0a read3 dif4_lsb 0x0b read4 dif5_msb 0x0c read5 dif5_lsb 0x0d read6 dif6_msb 0x0e read7 dif6_lsb 0x0f read8 dif7_msb
cy8cmbr2110 document number: 001-74494 rev. *a page 66 of 68 there are 25 debug data read registers (0x07-0x1f). hence, 25 byte s of space is available for one single read. therefore, if th e parameter 3 is selected, the raw count and baseline data of a maxi mum of six buttons can be read at a time. if there are ten bu ttons enabled in the design, then the host needs to read cs0 - cs5 first, and then change the button number (register number 0x01) to ?6? and read cs6 - cs9 information. if parameter 4 is select ed, all the parameters (raw count, baseline, differenc e count, parasitic capacitance, and snr) of the s elected button (from register 0x01) are written sequentially into the debug data read registers. 5.4 button_current_statx capsense button current status registers individual register names and addresses: reading from these registers give the button on/off status. 0x10 read9 dif7_lsb 0x11 read10 dif8_msb 0x12 read11 dif8_lsb 0x13 read12 dif9_msb 0x14 read13 dif9_lsb button_current_stat0: dd, 04h button_current_stat1: dd, 05h button_current_ stat0 765432 10 access: fd r: 0 r: 0 r: 0 r: 0 r: 0 r: 0 r: 0 r: 0 bit name cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 button_current_ stat1 76543210 access: fd r: 0 r: 0 bit name cs9 cs8 bit name description x csx this bit gives the button on/off status 0 button off 1 button on register register name value written to register
cy8cmbr2110 document number: 001-74494 rev. *a page 67 of 68 reference information acronyms document conventions units of measure numeric naming hexadecimal numbers are represented with all letters in uppercase with an appended lowercase 'h' (for example, '14h' or '3ah'). hexadecimal numbers may also be represented by a '0x' prefix, the c coding convention. binary numbers have an appended lowercase 'b' (for example, 01010100b' or '01000011b'). numbers not indicate d by an 'h', 'b', or 0x are decimal. acronym description ac alternating current ai analog input aio analog input/output aido analog input/digital output arst auto reset di digital input do digital output dio digital input/output p power pins c f finger capacitance c p parasitic capacitance cs capsense fss flanking sensor suppression gpo general purpose output i/o input/output led light emitting diode lsb least significant bit msb most significant bit pcb printed circuit board por power-on reset post power on self test qfn quad flat no-lead rf radio frequency snr signal to noise ratio units description c degree celsius k ? kilohm a microampere s microsecond ma milliampere mm millimeter mil one thousandth of an inch (1 mil = 0.0254 mm) ms millisecond mv millivolt na nanoampere nf nanofarad ns nanosecond ? ohm %percent pf picofarad vvolts
document number: 001-74494 rev. *a re vised september 4, 2012 page 68 of 68 all products and company names mentioned in this document may be the trademarks of their respective holders. cy8cmbr2110 ? cypress semiconductor corporation, 2012. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expe cted to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 document title: cy8cmbr2110 capsense ? express ? 10-button controller document number: 001-74494 revision ecn orig. of change submission date description of change ** 3698907 udyg 07/31/2012 new datasheet *a 3733388 udyg 09/04/2012 language edits. fmea feat ure - required button resistance mentioned ez-click hyperlink fixed move datasheet to final version

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